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Abstract: As more transistors are integrated onto larger dies, single-chip multiprocessors integrated with large amounts of cache memory will soon become a feasible alternative to the large, monolithic uniprocessors that dominate today's microprocessor marketplace. Hydra offers a promising way to build a small-scale MP-on-a-chip using a fairly simple design that still maintains excellent performance on a wide variety of applications. This report examines key parts of the Hydra design --- the memory... (Update)
Context of citations to this paper: More
...on an SMP, focusing on the memory system performance. Other investigations using SimOS do not investigate OS activity at all [28, 44, 27, 17]. Web servers have been the subject of only limited study, due to their relatively recent emergence as a workload of interest....
...episodes. 1. 2 Thread level parallelism As processor architects design chips that are capable of concurrently running multiple threads [47][19], and the cost of multiprocessor systems come into the reach of mainstream users [2] it is important to consider what role...
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0.2: A Single Chip Multiprocessor Integrated with High.. - Yamauchi, HAMMOND.. (1999) (Correct)
0.2: A Single Chip Multiprocessor Integrated with DRAM - Yamauchi, Hammond, Olukotun (1997) (Correct)
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4: Data speculation support for a chip multiprocessor (context) - Hammond, Willey et al. - 1998
3: The case for a SingleChip Multiprocessor (context) - Olukotun, Nayfeh et al. - 1996
3: Simultaneous multithreading: Maximizing on-chip parallelism - Tullsen, Eggers et al. - 1995
BibTeX entry: (Update)
L. Hammond and K. Olukotun, Considerations in the Design of Hydra: a Multiprocessor-on-a-Chip Microarchitecture, Stanford University Computer Systems Laboratory, Technical Report No. CSL-TR-98-749, Stanford University, February 1998. http://citeseer.ist.psu.edu/hammond98considerations.html More
@techreport{ hammond98considerations,
author = "Lance Hammond and Kunle Olukotun",
title = "Considerations in the Design of Hydra: {A} Multiprocessor-on-a-Chip Microarchitecture",
number = "CSL-TR-98-749",
pages = "13",
year = "1998",
url = "citeseer.ist.psu.edu/hammond98considerations.html" }
Citations (may not include all citations):1575 Computer Architecture: A Quantitative Approach (context) - Patterson, Hennessy - 1996
97 The Case for a Single Chip Multiprocessor (context) - Olukotun, Chang et al. - 1996
75 The MIPS R10000 superscalar microprocessor (context) - Yeager - 1996
38 Evaluation of Design Alternatives for a Multiprocessor Micro.. (context) - Nayfeh, Hammond et al. - 1996
12 The SUIF Compiler System: A Parallelizing and Optimizing Res.. (context) - Wilson, French et al. - 1994
9 The SimOS approach (context) - Rosenblum, Herrod et al. - 1995
9 A SingleChip Multiprocessor Integrated with DRAM - Yamauchi, Hammond et al. - 1997
5 A Shared Bus Control Mechanism and a Cache Coherence Protoco.. (context) - Takahashi, Takano et al. - 1996
1 Arthur Revitalizes PowerPC Line (context) - Gwennap - 1997
The graph only includes citing articles where the year of publication is known.
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REMARC: Reconfigurable Multimedia Array Coprocessor - Miyamori, Olukotun (1998) (Correct)
The Hierarchical Multi-Bank DRAM: A High-Performance.. - Yamauchi, Hammond.. (1997) (Correct)
A Single Chip Multiprocessor Integrated with High Density.. - Yamauchi, Hammond, Olukotun (1997) (Correct)
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