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Abstract: This thesis presents the design and implementation of the integer unit datapath found in the execution stage of the MAP cluster pipeline. It begins with a discussion of design flow and techniques before presenting the integer unit specification. Next, the integer unit architecture is developed. Finally, the design and implementation of each module within the integer unit is presented. Issues ranging from architecture to logic to circuits to layout are presented. Thesis Supervisor: William J.... (Update)
Context of citations to this paper: More
.... are examined in detail in two selected modules, the Integer Register Read stage Datapath (IRRDP) and the 64 bit Adder Subtracter [44] (ADDSUB) As the IRRDP is a predominantly regular structure, exploration of its different implementations provides insights to the...
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BibTeX entry: (Update)
Gupta, P. Design and implementation of the integer unit datapath of the map cluster of the m-machine. Master's project, Massachusetts Institute of Technology, EE/CS Department, May 1996. http://citeseer.ist.psu.edu/gupta96design.html More
@inproceedings{ gupta96design,
author = "Anshul Gupta and Fred G. Gustavson and Mahesh V. Joshi and Sivan Toledo",
title = "The Design, Implementation, and Evaluation of a Banded Linear Solver for Distributed-Memory Parallel Computers",
booktitle = "{PARA}",
pages = "328-340",
year = "1996",
url = "citeseer.ist.psu.edu/gupta96design.html" }
Citations (may not include all citations):159 Principles of CMOS VLSI Design: A Systems Perspective (context) - Weste, Eshraghian - 1993
3 Massachusetts Institute of Technology (context) - Hartman, implementation et al. - 1996
2 MIT Concurrent VLSI Architecture Memo (context) - Dally, Keckler et al. - 1994
1 Submitted to the 22nd annual international symposium on comp.. (context) - Fillo, Keckler et al. - 1994
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