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A High-level Interconnect Power Model for Design Space Exploration (2003)  (Make Corrections)  
Pallav Gupta, Lin Zhong, N. K. Jha



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Abstract: In this paper, we present a high-level power model to estimate the power consumption in semi-global and global interconnects. Such interconnects are used for communications between logic modules, clock distribution networks, and power supply rails. The main purpose of our model is to set forward a simple methodology to efficiently obtain first-order estimates of interconnect power in early stages of the design process. Hence, the objective is to provide designers and/or high-level design... (Update)

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BibTeX entry:   (Update)

@misc{ gupta-highlevel,
  author = "Pallav Gupta and Lin Zhong and N. K. Jha",
  title = "A High-level Interconnect Power Model for Design Space Exploration",
  url = "citeseer.ist.psu.edu/gupta03highlevel.html" }
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63   A stochastic wire-length distribution for gigascale integrat.. (context) - Davis, De and et al. - 1998
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32   High-level Power Analysis and Optimization (context) - Raghunathan, Jha et al. - 1998
15   SCALP: An iterative-improvement based low power data path sy.. (context) - Raghunathan, Jha - 1997
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3   Interconnect-aware high-level synthesis for low power - Zhong, Jha - 2002
3   chip wiring design challenges for gigahertz operation (context) - Deutsch - 2001
2   Interconnect energy dissipation modeling in high-speed ULSI .. (context) - Heydari, Pedram - 2002
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Interconnect-aware High-level Synthesis for Low Power - Lin Zhong And (2002)   (Correct)
Rejection Based On A Posteriori Probability Estimated By Mlp.. - Zhong, Liu, Liu (2000)   (Correct)
Dynamic Power Optimization of Interactive Systems - Zhong, Jha (2004)   (Correct)

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