The cache coherence protocol plays an important role in the performance of a distributed shared-memory (DSM) multiprocessor. A variety of cache coherence protocols exist and differ mainly in the scope of the sites that are updated by a write operation. These protocols can be complex and their impact on the performance of a multiprocessor system is often difficult to assess. To obtain good performance, both architects and users must understand processor communication, data locality, the properties of the interconnection network, and the nature of the coherence protocols. Analyzing the processor data sharing behavior and determining its effect on cache coherence communication traffic is the first step to a better understanding of overall performance. Toward this goal, this dissertation provides a framework for evaluating the coherence communication traffic of different protocols and considers using more than one protocol in a DSM multiprocessor. The framework consists of a data access characterization and the application of assessment rules. Its usefulness is demonstrated through an investigation into the performance of different cache coherence protocols for a variety of systems and parameters. It is shown to be effective for determining the relative performance of protocols and the effect of changes in system and
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