VIPER: A VLIW integer microprocessor (1993) [11 citations — 0 self]
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by Jeffrey Gray, Andrew Naylor, Arthur Abnous, Nader Bagherzadeh
IEEE Journal of Solid State Circuits
http://www.eng.uci.edu/comp.arch/papers/viper/jssc/jssc.ps
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@ARTICLE{Gray93viper:a,author = {Jeffrey Gray and Andrew Naylor and Arthur Abnous and Nader Bagherzadeh},
title = {VIPER: A VLIW integer microprocessor},
journal = {IEEE Journal of Solid State Circuits},
year = {1993},
volume = {28},
pages = {1377--1383}
}
Years of Citing Articles
Abstract:
This paper describes the design and implementation of a very long instruction word (VLIW) microprocessor. The VIPER (VLIW integer processor) contains four pipelined functional units, and can achieve 0.25 cycle-per-instruction performance. The processor is capable of performing multiway branch operations, two load/store operations or up to four ALU operations in each clock cycle, with full register file access to each functional unit. Designed in twelve months, the processor is integrated with an instruction cache controller and a data cache, requiring 450,000 transistors and a die size of 12.9 by 9.1 mm in a 1.2 m technology. 1
Citations
| 3381 | Computer Architecture: A Quantitative Approach – Hennessy, Patterson - 1996 |
| 171 | A VLIW Architecture for a Trace Scheduling Compiler – Colwell, Nix, et al. - 1987 |
| 136 | A case for direct-mapped caches – Hill - 1988 |
| 53 | Some Design Ideas for a VLIW Architecture for Sequential-Natured Software – Ebcioglu - 1988 |
| 22 | Compaction-based parallelization – Aiken - 1988 |
| 8 | CREATE-LIFE: A Modular Design Approach for High Performances ASIC's – Labrousse, Slavenburg - 1990 |
| 7 | Architectural Design and Analysis of a VLIW Processor – Abnous, Bagherzadeh - 1995 |
| 1 | VLSI Design of the TinyRISC Microprocessor – Abnous, Christensen, et al. - 1992 |
| 1 | A CMOS RISC CPU Designed for High Performance on Large Applications – Lotz, Miller, et al. - 1990 |
