RISC processor and System-on-a-
Abstract:
This month, he explores the CPU pipeline and designs the control unit. Listen up, because next month, he’ll tie it all together. www.circuitcellar.com l ast month, I discussed the instruction set and the datapath of an xr16 16-bit RISC processor. Now, I’ll explain how the control unit pushes the datapath’s buttons. Figure 2 in Part 1 (Circuit Cellar, 116) showed the CTRL16 control unit schematic symbol in context. Inputs include the RDY signal from the memory controller, the next instruction word INSN from memory, and 15:0 the zero, negative, carry, and overflow outputs from the datapath. The control unit outputs manage the datapath. These outputs include pipeline control clock enables, register and operand selectors, ALU controls, and result multiplexer output enables. Before designing the control circuitry, first consider how the pipeline behaves in both good and bad times. PIPELINED EXECUTION To increase instruction throughput, the xr16 has a three-stage pipeline—instruction fetch (IF), decode and operand fetch (DC), and execute (EX).
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