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Abstract: With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the performance of an individual program. However, with such speculatively-parallel execution the cache locality once enjoyed by the original uniprocessor execution is significantly disrupted: for TLS execution on a four-processor CMP, we find that the data-cache miss rates are nearly four-times those of the uniprocessor case,... (Update)
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BibTeX entry: (Update)
S. Fung and J. G. Steffan. Improving cache locality for thread-level speculation. In IPDPS 20, April 2006. http://citeseer.ist.psu.edu/fung05improving.html More
@misc{ fung06improving,
author = "S. Fung and J. Steffan",
title = "Improving cache locality for thread-level speculation",
text = "S. Fung and J. G. Steffan. Improving cache locality for thread-level speculation.
In IPDPS 20, April 2006.",
year = "2006",
url = "citeseer.ist.psu.edu/fung05improving.html" }
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http://www.spechbench.org
Documents on the same site (http://www.eecg.toronto.edu/~steffan/publications.html): More
Extending Cache Coherence to Support Thread-Level Data.. - Steffan, Colohan, Mowry (1998) (Correct)
Generating Network Topologies That Obey Power Laws - Palmer, Steffan (2000) (Correct)
Improving Value Communication for Thread-Level Speculation - Steffan, Colohan, Zhai.. (2002) (Correct)
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