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The Energy Efficiency of IRAM Architectures (1996)  (Make Corrections)  (37 citations)
Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce McGaughy, David Patterson, Tom Anderson, Katherine Yelick
ISCA



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Abstract: Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more energy efficient than conventional systems. The high density of DRAM permits a much larger amount of memory on-chip than a traditional SRAM cache design in a logic process. This allows most or all IRAM memory accesses to be satisfied on-chip. Thus there is much less need to drive high-capacitance off-chip buses, which... (Update)

Context of citations to this paper:   More

.... of the memory system is also reduced, as most memory accesses can be processed on chip, without driving high capacitance board traces [25]. Embedded DRAM is at least five times denser than SRAM. One can integrate a processor with a DRAM memory system large enough to be...

.... capability to take the energy consumed by accesses to off chip memory into account using models taken from the IRAM project at Berkeley [6]. We have also modified SimpleScalar Wattch to extract information about how many of the level 2 cache accesses that originates from...

Cited by:   More
Multiplier for VIRAM1 - Joseph Gebis Report   (Correct)
Integrating Processor Slowdown and Preemption Threshold.. - Jejurikar, Gupta (2004)   (Correct)
An Adaptive Chip-Multiprocessor Architecture for Future.. - Nikitovic, Brorsson   (Correct)

Active bibliography (related documents):   More   All
1.5:   The Performance of Applications and Operating Systems on.. - Bowman, Cardwell, Romer   (Correct)
0.8:   Hardware Techniques To Improve The Performance Of The.. - Burger (1998)   (Correct)
0.8:   Embedded DRAM Architectural Trade-Offs - Norbert Wehn Sren (1998)   (Correct)

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0.5:   Scalable Processors in the Billion-Transistor Era: IRAM - Kozyrakis, Perissakis.. (1997)   (Correct)
0.5:   Scaling Processors to 1 Billion Transistors and Beyond: .. - Perissakis, Kozyrakis, ..   (Correct)
0.4:   Intelligent RAM (IRAM): the Industrial Setting.. - Patterson..   (Correct)

Related documents from co-citation:   More   All
12:   Computer Architecture: a Quantitative Approach (context) - Hennessy, Patterson - 1996
7:   Missing the Memory Wall: The Case for Processor/Memory Integration (context) - Saulsbury, Pong et al. - 1996
7:   A Case for Intelligent RAM: IRAM - Patterson, Anderson et al. - 1997

BibTeX entry:   (Update)

Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce McGaughy, and David Patterson. The Energy Efficiency of IRAM Architectures. Technical report, University of California at Berkeley, Department of Computer Science, November 1996. To be published in ISCA97. http://citeseer.ist.psu.edu/fromm96energy.html   More

@inproceedings{ fromm97energy,
    author = "Richard Fromm and Stylianos Perissakis and Neal Cardwell and Christoforos E. Kozyrakis and Bruce McGaughy and David A. Patterson and Thomas E. Anderson and Katherine A. Yelick",
    title = "The Energy Efficiency of {IRAM} Architectures",
    booktitle = "{ISCA}",
    pages = "327-337",
    year = "1997",
    url = "citeseer.ist.psu.edu/fromm96energy.html" }
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56   A case for Intelligent RAM: IRAM - PATTERSON - 1997
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The graph only includes citing articles where the year of publication is known.


Documents on the same site (http://iram.cs.berkeley.edu/publications.html):   More
Evaluation of Existing Architectures in IRAM Systems - Bowman, Cardwell.. (1997)   (Correct)
Intelligent RAM (IRAM): the Industrial Setting.. - Patterson..   (Correct)
Efficient FFTs on IRAM - Thomas, Yelick   (Correct)

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