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Abstract: This paper describes the theory and implementation of a novel system for hardware synthesis from requirement specifications expressed in a graphical specification language called Symbolic Timing Diagrams (STD). The system can be used together with an existing formal--verification environment for VHDL leading to a novel methodology based on the combination of synthesis and formal verification. We show the feasibility of the approach and experimental results obtained with the system on the well... (Update)
Context of citations to this paper: More
...of groups, and exponential growth is only encountered in the maximal size of the individual groups. Table 2 provides empiric results from [8], obtained by Feyerabend and Schlor when using both the non compositional and the compositional synthesis procedure of ICOS for...
...widely used in electrical engineering. Visual Temporal Logic as a Rapid Prototyping Tool 3 Req Ack Req Req Req Ack Ack Ack [1,5] [2,4] 2,4] 0,10] Fig. 1. An RTSTD specifying a simple handshaking protocol. The black arcs represent strong constraints, while weak...
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BibTeX entry: (Update)
@misc{ dept-hardware,
author = "Konrad Feyerabend Dept",
title = "Hardware Synthesis from Requirement Specifications",
url = "citeseer.ist.psu.edu/feyerabend96hardware.html" }
Citations (may not include all citations):374 Automata on infinite objects (context) - Thomas - 1992
110 the synthesis of a reactive module (context) - Pnueli, Rosner - 1989
31 Formal Development of Reactive Systems (context) - Lewerenz, Lindner - 1994
29 Specification and verification of VHDL-based system-level ha.. (context) - Damm, Josko et al. - 1995
17 Integrating behavior and timing in executable specifications (context) - Khordoc, Dufresne et al. - 1993
12 Transformation of timing diagram specifications into VHDL co.. (context) - Grass, Grobe et al. - 1995
10 System-level Synthesewerkzeuge : von der Theorie zur Anwendu.. (context) - Korf - 1996
8 Formalized timing diagrams (context) - Boriello - 1992
6 High-level modelling using extended timing diagrams (context) - Moeschler, Amann et al. - 1993
6 Interface controller synthesis from requirement specificatio.. (context) - Korf, Schlor - 1994
5 Formal Methods for Hardware Verification (context) - Kloos, Goicolea et al. - 1996
3 Schaltungssynthese aus Zeitdiagrammen: Eine Kopplung des ICO.. (context) - Feyerabend - 1996
2 Schwerpunktprogramm 'Rapid Prototyping fur integrierte Steue.. (context) - Forschungsgemeinschaft - 1996
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