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Abstract: Branch target buffers, or BTBs, are small caches for program branching information. Like data caches, addresses are divided into equivalence classes based on their low order bits. Unlike data caches, however, complete resolution of a single address from within an equivalence class is not required for correct execution. Substantial savings are therefore possible by employing partial resolution, using fewer tag bits than necessary to uniquely identify an address. We present the... (Update)
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...Both reductions are shown in Fig. 1. Reduction of tag fields is known as partial resolution and has been proposed by Fagin and Russell [8]. The main contribution of this paper is target field size reduction. We make use of branch locality, i.e. most branch distances are...
...from the SPEC95 integer suite. The instruction address length is 30 bits. The tag reduction scheme proposed by Fagin and Russeell [1] is used. The baseline conventional BTB consists of a 2048 entry, 2 way set associative table. The evaluated two level scheme has the BTB...
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BibTeX entry: (Update)
B. Fagin and K. Russell, "Partial Resolution in Branch Target Buffers," Proc. 28th Ann. Int'l Symp. Microarchitecture, pp. 193-198, Ann Arbor, Mich., Dec. 1995. http://citeseer.ist.psu.edu/fagin97partial.html More
@article{ fagin97partial,
author = "Barry S. Fagin",
title = "Partial Resolution in Branch Target Buffers",
journal = "IEEE Transactions on Computers",
volume = "46",
number = "10",
pages = "1142-1145",
year = "1997",
url = "citeseer.ist.psu.edu/fagin97partial.html" }
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