(Enter summary)
Abstract: . Most modern wide-address computer architecture do not prescribe a
page table format, but instead feature a software-loaded TLB, which gives the
operating system complete flexibility in the implementation of page tables. Such
flexibility is necessary, as to date no single page table format has been established
to perform best under all loads. With the recent trend to kernelised operating
systems, which rely heavily on mapping operations for fast data movement across
address-spaces,... (Update)
Context of citations to this paper: More
...In the first category are studies that have explored different page table structures, page sizes and superpages. Elphinstone [4, 5] has done extensive studies on how different page table structures influence TLB and overall system performance. His work was directed at...
...of the two formats. Past studies have compared the performance of different page tables on architectures with software loaded TLBs 94,EHL99,DMY99] or used trace driven analysis of changing the page table format in an otherwise unmodified architecture...
Cited by: More
A Physically-Addressed L4 Kernel - Nourai (2005)
(Correct)
Itanium Page Tables and TLB - Chapman, Wienand, Heiser (2003)
(Correct)
Enhancing IA-64 Memory Management - Au, Heiser (2000)
(Correct)
Active bibliography (related documents): More All
1.1: Page Tables for 64-Bit Computer Systems - Elphinstone, Heiser (1998)
(Correct)
0.8: The Mungi Single-Address-Space Operating System - Heiser, Elphinstone.. (1998)
(Correct)
0.4: Virtual Memory In A 64-Bit Microkernel - Elphinstone (1999)
(Correct)
Similar documents based on text: More All
1.5: Guarded Page Tables on the MIPS R4600 - Jochen Liedtke Gmd (1995)
(Correct)
0.8: L4 Reference Manual MIPS R4x00 Version 1.0 Kernel Version.. - School Of Computer
(Correct)
0.7: L4 Reference Manual Alpha 21x64 - Potts, Winwood, Heiser (2001)
(Correct)
Related documents from co-citation: More All
4: Intel, The IA-64 Architecture Software Developer's Manual Vol. 2 rev. 1.1: Itanium (TM); System Architecture, Intel, 2000, Volume 2, Chapter 13, \Coherence and MP Ordering." http://developer.intel.com/design/ ia-64/downloads/24531802.htm.
3: School of Computer Science and Engineering (context) - Elphinstone, Heiser et al. - 1997
2: Improving the address translation performance of widely shared pages
- Khalidi, Talluri - 1995
BibTeX entry: (Update)
Kevin Elphinstone, Gernot Heiser, and Jochen Liedtke. Page tables for 64-bit computer systems. In Proceedings of the 4th Australasian Computer Architecture Conference (ACAC), pages 211--226, Auckland, New Zealand, January 1999. Springer Verlag. Available from URL http://www.cse.unsw.edu.au/disy/papers/. http://citeseer.ist.psu.edu/elphinstone99page.html More
@inproceedings{ elphinstone99page,
author = "Kevin Elphinstone and Gernot Heiser",
title = "Page Tables for 64-Bit Computer Systems",
booktitle = "Australasian Computer Architecture Conference, Auckland, New Zealand",
publisher = "Springer-Verlag, Singapore",
pages = "211--226",
year = "1999",
url = "citeseer.ist.psu.edu/elphinstone99page.html" }
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