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Abstract: . The paper treats the problem of automatic generation of communication interfaces between hardware devices such as FPGAs and ASICs and software (programmable) devices such as microprocessors. In [2], we introduced an object-oriented approach to interface generation starting from a coarse-grain process graph specification level to the final device-dependent implementation. Here, we present generic templates of how to implement hardware/software interfaces, in particular in the scope of rapid... (Update)
Context of citations to this paper: More
...to ports. The ports are characterized by their bit width and use handshake signals to implement an asynchronous communication protocol [4]. On termination, a task raises its done flag. Queues are bu#ers with FIFO semantics that connect two tasks. Directly connected tasks...
.... our institute we develop synthesis tools like CCS (Communication Channel Synthesis) HASIS (Hardware Software Interface Synthesis) [4, 2, 3], and CORES (Con gurator for Recon gurable Embedded Systems) 6, 1] to automatically generate interfaces and device drivers for various...
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ProGram: A Grammar-Based Method for Specification and Hardware.. - Öberg (1999) (Correct)
Towards Device Driver Synthesis - Lehmann (2002) (Correct)
CoFrame: A Modular Co-Design Framework for.. - Eisenring, Zitzler.. (Correct)
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0.3: Communication Synthesis for Reconfigurable Embedded Systems - Eisenring, Platzner, Thiele (1999) (Correct)
0.3: Domain-Specific Interface Generation from Dataflow.. - Eisenring, Teich (1998) (Correct)
0.1: Concurrency-Oriented Optimization for Low-Power Asynchronous.. - Plana, Nowick (1996) (Correct)
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0.2: Orthogonal Partitioning and Gated Clock Architecture for .. - Shelar, Narayanan, Desai (2000) (Correct)
0.2: Rapid Prototyping of Dataflow Programs on.. - Eisenring, Teich, Thiele (1998) (Correct)
0.1: System-Level Synthesis Using Evolutionary Algorithms - Blickle, Teich, Thiele (1998) (Correct)
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5: Domain-specific interface generation from dataflow specifications - Eisenring, Teich - 1998
3: Rapid prototyping of communication architectures (context) - Kirschbaum, Glesner - 1997
3: An object-oriented communication library for hardware-software co-design - Vahid, Tauro - 1997
BibTeX entry: (Update)
M. Eisenring and J. Teich. Interfacing hardware and software. In 8th International Workshop on Field-Programmable Logic and Applications, FPL'98, Lecture Notes in Computer Science, 1482, pages 520 -- 524, Tallinn, Estonia, Aug. 31 - sept. 3 1998. http://citeseer.ist.psu.edu/eisenring98interfacing.html More
@inproceedings{ eisenring98interfacing,
author = "M. Eisenring and J. Teich",
title = "Interfacing Hardware and Software",
booktitle = "Field-Programmable Logic: From {FPGA}s to Computing Paradigm",
month = "/",
publisher = "Springer-Verlag, Berlin",
editor = "Reiner W. Hartenstein and Andres Keevallik",
pages = "520--524",
year = "1998",
url = "citeseer.ist.psu.edu/eisenring98interfacing.html" }
Citations (may not include all citations):210 Synchronous dataflow (context) - Lee, Messerschmitt - 1987
30 Constructing application-specific heterogeneous embedded arc.. - Lin, Vercauteren et al. - 1996
24 Transformation and synthesis of FSMs for low-power gated-clo.. - Benini, De Micheli - 1995 ACM
16 Domain-specific interface generation from dataflow specifica.. - Eisenring, Teich - 1998 ACM
15 Single-Rail Handshake Circuits (context) - Peeters - 1996 ACM
3 Rapid prototyping of dataflow programs on hardware/software .. - Eisenring, Teich et al. - 1998 ACM
1 Low-power globally asynchronous local synchronous design usi.. (context) - Jou, Chuang - 1997
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www-date.uni-paderborn.de/publications.html): More
An Evolutionary Approach to System-Level Synthesis - Teich, Blickle, Thiele (1997) (Correct)
System-Level Synthesis Using Evolutionary Algorithms - Blickle, Teich, Thiele (1996) (Correct)
Performance Analysis of Mixed Asynchronous Synchronous.. - Teich, Sriram, Thiele.. (1994) (Correct)
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