Carl Ebeling  Home/Search
Context
Related
| washington.edu/tr/...WCSE020601.pdf Cached: PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
PS.gz PS Image Update HelpFrom: washington.edu/resea...trbyname (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: This document describes a proposed approach to compiling high-level language programs to the Rapid configurable architecture. Since the general version of Rapid very broad, this approach should be applicable to a wide range of coarse-grained configurable architectures. The compiler is comprised of a standard compiler front-end and a backend scheduler based on a simultaneous place and route formulation of the problem. This will allow the many constraints of a configurable architecture to be... (Update)
Active bibliography (related documents): More All
0.9: The General Rapid Architecture Description - Ebeling (2002) (Correct)
0.5: Algorithmic and Theoretical Problems Related to the Physical.. - Karro (2000) (Correct)
0.3: Data-Parallel Digital Signal Processors: Algorithm Mapping.. - Rajagopal (2004) (Correct)
Similar documents based on text: More All
0.1: Mesh Routing Topologies for Multi-FPGA Systems - Hauck, Borriello, Ebeling (1998) (Correct)
0.1: RaPiD - A Configurable Computing Architecture for.. - Ebeling.. (1996) (Correct)
0.1: QoSOS: An Adaptable Architecture for QoS.. - Moreno, Neto.. (2003) (Correct)
BibTeX entry: (Update)
@misc{ ebeling-compiling,
author = "Carl Ebeling",
title = "Compiling for Coarse-Grained Adaptable Architectures",
url = "citeseer.ist.psu.edu/ebeling02compiling.html" }
Citations (may not include all citations):353 Software pipelining : an effective scheduling technique for .. (context) - Lam - 1988
294 A loop transformation theory and an algorithm to maximize pa.. (context) - Wolf, Lam - 1991
176 Garp: A MIPS Processor with a Reconfigurable Coprocessor - Hauser, Wawrzynek - 1997
158 Effective compiler support for predicated execution using th.. - Mahlke - 1992
157 Conversion of control dependence to data dependence (context) - Allen, Kennedy et al. - 1983
150 Iterative modulo scheduling: An algorithm for software pipel.. - Rau - 1994
138 The high-level synthesis of digital systems (context) - McFarland, Parker et al. - 1990
124 Synthesis and Optimization of Digital Circuits (context) - Micheli - 1994
109 A High-Performance Microarchitecture with Hardware-Programma.. - Razdan, Smith - 1994
71 Space-Time Scheduling of Instruction-Level Parallelism on a .. - Lee, Barua et al. - 1998
66 OneChip: An FPGA Processor with Reconfigurable Logic - Wittig, Chow - 1996
63 PipeRench: A Coprocessor for Streaming Multimedia Accelerati.. - Goldstein, Schmit et al. - 1999
47 JHDL - an HDL for reconfigurable systems - Bellows, Hutchings - 1998
40 An Efficient General Cooling Schedule for Simulated Annealin.. (context) - Huang, Romeo et al. - 1986
36 A Design Space Evaluation of Grid Processor Architectures - Nagarajan, Sankaralingam et al. - 2001
32 MATRIX: A Reconfigurable Computing Architecture with Configu.. - Mirsky, Dehon - 1996
31 Architecture Design of Reconfigurable Pipelined Datapaths - Cronquist, Franklin et al. - 1999
30 Placement and Routing Tools for the Triptych FPGA - Ebeling, McMurchie et al. - 1995
29 Mapping Applications to the RaPiD Configurable Architecture - Ebeling, Cronquist et al. - 1997
26 Instruction level parallelism for reconfigurable computing - Callahan, Wawrzynek - 1998
26 Optimization by simulated annealing (context) - Kirpatrick, Gelatt et al. - 1983
26 Specifying and Compiling Applications for RaPiD - Cronquist, Franklin et al. - 1998
24 Compiler Technology for Future Microprocessors - Hwu, Hank et al. - 1995
23 Algorithms for Hardware Allocation in Data Path Synthesis (context) - Devadas, Newton - 1989
20 CHIMAERA: A High-Performance Architecture with a Tightly-Cou.. - Ye, Banerjee et al. - 2000
15 Stream computations organized for Reconfigurable execution - Caspi, Chu et al. - 2000
11 A DAG-Based Design Approach for Reconfigurable VLIW Processo.. - Alippi - 1999
9 hierarchical synchronous reconfigurable array (context) - Tsu, Macy et al. - 1999
9 Compiling Hybrid RISCFPGA Architecture (context) - Compiling, RISC et al.
7 Language Reference Guide (context) - Aubury, Page et al. - 1996
6 Performance-driven simultaneous place and route for FPGAs (context) - Nag, Rutenbar - 1998
6 The MorphoSys Parallel Reconfigurable System - Lu, Singh et al. - 1999
5 High level synthesis for designing custom computing hardware - Doncev, Leeser et al. - 1998
3 An Emulator for Exploring RaPiD Configurable Computing Archi.. (context) - Fisher, Rennie et al. - 2001
2 Pathfinder: A Negotiation-Based Router for Routing-Constrain.. (context) - Ebeling, McMurchie - 1995
1 Distributed-memory parallel routing for fieldprogrammable ga.. (context) - Chan, Schlag et al. - 2000
1 The Common Language Encoding Form (context) - Weaver, Cahoon et al.
Documents on the same site (http://www.cs.washington.edu/research/tr/tr-by-name.html): More
A Multiresolution Framework for Dynamic Deformations - Capell, Green, Curless.. (2002) (Correct)
Composing Dataflow Analyses and Transformations - Lerner, Grove, Chambers (2001) (Correct)
A Bilinear Model for Sparse Coding - Grimes, Rao (2002) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC