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Abstract: Software pipelining for instruction-level parallel computers with non-blocking caches usually assigns memory access latency by assuming either all accesses are cache hits or all are cache misses. We contend setting memory latencies by cache reuse analysis leads to better software pipelining than either an all-hit or all-miss assumption. Using a simple cache-reuse model, our software pipelining optimization achieved 10% improved execution performance over assuming all-cache-hits and used... (Update)
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BibTeX entry: (Update)
Chen Ding, Steve Carr, and Phil Sweany. Modulo scheduling with cache reuse information. In Proceedings of EuroPar '97, pages 1079--1083, August 1997. http://citeseer.ist.psu.edu/ding97modulo.html More
@inproceedings{ ding97modulo,
author = "Chen Ding and Steve Carr and Philip H. Sweany",
title = "Modulo Scheduling with Cache Reuse Information",
booktitle = "European Conference on Parallel Processing",
pages = "1079-1083",
year = "1997",
url = "citeseer.ist.psu.edu/ding97modulo.html" }
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162 Improving data locality with loop transformations - McKinley, Carr et al. - 1996
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40 Iterative modulo scheduling (context) - Rau - 1994
21 Predictability loadstore instruction latencie (context) - Windheiser, Gupta et al. - 1993
1 Software pipelining with cache-reuse information (context) - Ding, Carr et al. - 1996
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