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Abstract: As microprocessor speeds increase, memory bandwidth is increasingly the performance bottleneck for microprocessors. This has occurred because innovation and technological improvements in processor design have outpaced advances in memory design. Most attempts at addressing this problem have involved hardware solutions. Unfortunately, these solutions do little to help the situation with respect to current microprocessors. In previous work, we developed, implemented, and evaluated an algorithm... (Update)
Context of citations to this paper: More
...cache performance [14, 6, 15] However, none of these transformations result in space savings. Existing compression transformations [10, 7] rely upon compile time analysis to prove that certain data items do not require a complete word of memory. They are applicable only...
...entity from inputbuffer. The second example illustrates the packing of a 5 bit entity taken from LARc[2] with a 3 bit entity taken from LARc[3]. Unpacking: delta = inputbuffer 4) 0xf Packing: c = LARc[2] 0x1f) 3)j ( LARc[3] 2) 0x7) In addition to the...
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BibTeX entry: (Update)
J. Davidson and S. Jinturkar. Memory access coalescing: A technique for eliminating redundant accesses. In Proceedings of PLDI, June 1994. http://citeseer.ist.psu.edu/davidson94memory.html More
@inproceedings{ davidson94memory,
author = "Jack W. Davidson and Sanjay Jinturkar",
title = "Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses",
booktitle = "{SIGPLAN} Conference on Programming Language Design and Implementation",
pages = "186-195",
year = "1994",
url = "citeseer.ist.psu.edu/davidson94memory.html" }
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