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Abstract: We present a new temporal logic, GTL, appropriate for specifying properties of hardware at the register transfer level. We argue that this logic represents an improvement over model checking for some natural hardware verification problems. We show that the validity problem for this logic is \Pi 1 1 complete. We then identify a fragment of the logic that is decidable. We show that in this fragment we are still able to encode many interesting problems, including the correctness of pipelined... (Update)
Context of citations to this paper: More
...of exploring their infinitely many possible evaluations. For model checking hardware systems, uninterpreted functions are used in [BD94,CN94] In our work, we follow the second direction: We introduce a notion for abstract types in the ASM SL. We regard models that comprise...
...and HDDs [7] have been developed to represent arithmetic functions more compactly than ROBDDs. There also emerged a number of methods [8, 5, 11] which verify the overall functionality of Register Transfer Level designs at an abstract level, using abstract variables to denote...
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BibTeX entry: (Update)
D. Cyrluk and P. Narendran. Ground temporal logic---a logic for hardware verification. In David Dill, editor, Computer-Aided Verification, CAV '94, volume 818 of Lecture Notes in Computer Science, pages 247--259, Stanford, CA, June 1994. Springer-Verlag. http://citeseer.ist.psu.edu/cyrluk94ground.html More
@inproceedings{ cyrluk94ground,
author = "{D. Cyrluk} and {P. Narendran}",
title = "Ground Temporal logic: {A} Logic for Hardware verification",
booktitle = "Proceedings of the sixth International Conference on Computer-Aided Verification {CAV}",
volume = "818",
publisher = "Springer-Verlag",
address = "Standford, California, USA",
editor = "{David L. Dill}",
pages = "247--259",
year = "1994",
url = "citeseer.ist.psu.edu/cyrluk94ground.html" }
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295 PVS: A prototype verification system (context) - Owre, Rushby et al. - 1992
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154 Simplification by cooperating decision procedures (context) - Nelson, Oppen - 1979
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71 Techniques for Automatic Verification of Real-time Systems (context) - Alur - 1991
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47 Formal verification of a pipelined microprocessor (context) - Srivas, Bickford - 1990
43 Verification of concurrent programs: A temporal proof system (context) - Manna, Pnueli - 1983
38 Automated verification of pipelined microprocessor control (context) - Burch, Dill - 1994
36 The existence of refinement mappings (context) - Abadi, Lamport - 1988
36 Digital Systems Research Center (context) - Lamport, logic et al. - 1991
33 Microprocessor verification in PVS: A methodology and simple.. - Cyrluk - 1993
28 The mechanical verification of a microprocessor design (context) - Hunt - 1986
23 Using transformations and verification in circuit design (context) - Saxe, Garland et al. - 1991
20 Half-order modal logic: How to prove real-time properties - Henzinger - 1990
16 Proving a computer correct in higher order logic (context) - Joyce, Birtwistle et al. - 1986
15 Verification of multiprocessor cache protocol using simulati.. (context) - Loewenstein, Dill - 1991
12 volume 8 of EATCS Monographs on Theoretical Computer Science (context) - Kroger, of - 1987
9 Formal hardware verification by symbolic trajectory evaluati.. (context) - Bryant, Beatty et al. - 1991
3 Hardware proofs using LCF-LSM and ELLA (context) - Cullyer, Pygott - 1985
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