Venkatesh Akella and Ganesh Gopalakrishnan. Static analysis techniques for the synthesis of efficient asynchronous circuits. Technical Report UUCS-91-018, Dept. of Computer Science, University of Utah, Salt Lake City, UT 84112, 1991. Home/Search Document Not in Database Summary Related Articles Check |
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Asynchronous Circuit Verification Using Trace Theory and CCS - Gopalakrishnan (1995) Self-citation (Gopalakrishnan) (Correct)
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Venkatesh Akella and Ganesh Gopalakrishnan. Static analysis techniques for the synthesis of efficient asynchronous circuits. Technical Report UUCS-91-018, Dept. of Computer Science, University of Utah, Salt Lake City, UT 84112, 1991.
Dynamic Reordering of High Latency Transactions in.. - Liebchen, Gopalakrishnan (1992) Self-citation (Gopalakrishnan) (Correct)
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Venkatesh Akella and Ganesh Gopalakrishnan. Static analysis techniques for the synthesis of efficient asynchronous circuits. Technical Report UUCS-91-018, Dept. of Computer Science, University of Utah, Salt Lake City, UT 84112, 1991. To appear in TAU '92: 1992 Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Princeton, NJ, March 18--20, 1992.
Specification and Validation of Control Intensive ICs in hopCP - Akella, Gopalakrishnan (1994) (1 citation) Self-citation (Akella Gopalakrishnan) (Correct)
....INTENSIVE ICS IN HOPCP 21 ffl A compiled code behavioral simulator to establish functional correctness of the hopCP specifications. In section 5.1, we introduce the algorithm parComp. In section 5.2, we will briefly introduce the seriality checking algorithm. These algorithms have been detailed in [2]. Section 5.3 presents the compiled code functional simulator that can be used to debug hopCP descriptions. Section 5.4 presents how hopCP specifications are debugged using tester processes. 5.1 Behavioral Inference via Parallel Composition In this section we will briefly introduce parComp and ....
....the set of reachable configurations from the initial states and determining if the two actions in questions can be enabled simultaneously or not. All the phases of the seriality checking procedure have been formalized and implemented in the hopCP design environment. The details are presented in [2]. This procedure was particularly useful on the USART specification because of its complexity. Several errors in the unsafe usage of the asynchronous ports were revealed. In addition we also discovered that the in practice we do not need separate channels for indata , inctrl , readdata and ....
Akella, V., and Gopalakrishnan, G. Static Analysis Techniques for the Synthesis of Efficient Asynchronous Circuits. Tech. Rep. UUCS-91-018, Department of Computer Science, University of Utah, Oct. 1991.
SHILPA: A High-Level Synthesis System for Self-timed Circuits - Akella, Gopalakrishnan (1992) (19 citations) Self-citation (Akella Gopalakrishnan) (Correct)
....such a design framework. The hopCP based design environment proposed in this paper, takes its input descriptions in a mixed process functional HDL tailored for hardware design called hopCP. It is comprised of a set of tools for analyzing and optimizing hopCP descriptions called parComp and conCur [5] a compiled code concurrent functional simulator, a synthesis tool called SHILPA to translate hopCP behavioral descriptions into self timed hardware, a library of self timed macrocells, and an interface to Viewlogic tools for simulation and implementation. All the tools in the hopCP design ....
....in general due to the use of data dependent communication guards) This information is useful in resource sharing, optimal guard evaluation, and for checking for the safe usage of shared variables i.e. flagging concurrent reads and writes on shared variables. Details of conCur are presented in [5]. Applications of conCur in the synthesis of self timed circuits will be described in this paper. SHILPA is based on a set of graph transformations that translate HFGs into normal form HFGs (NHFGs) We call this procedure action refinement. A NHFG is a HFG in which all the actions are of the form ....
Akella, V., and Gopalakrishnan, G. Static Analysis Techniques for the Synthesis of Efficient Asynchronous Circuits. Tech. Rep. UUCS-91-018, Department of Computer Science, University of Utah, 1992. Appears in the Second ACM/IEE Workshop on Timing Aspects of VLSI, TAU-92, Princeton, March 1992.
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