JamesLaudon, AnoopGupta, and Mark Horowitz. Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations. In Proceedings of the Sixth International Conferenceon Architectural Support for Programming Languages and Operating Systems, pages 308--318. ACM Press, October 1994.  Home/Search   Document Not in Database   Summary   Related Articles

....benchmarks in which synchronization performance is critical. 1 Introduction Parallel processor performance is critically tied to the mechanisms provided for tolerating long latencies that occur during remote memory accesses, and processor synchronization operations. Multiple context processors [20, 3, 13, 15] provide multiple register sets to multiplex several threads over a processor pipeline in order to tolerate these communication and synchronization latencies. Multiple register sets, including multiple instruction pointers, allow the state of multiple threads to be loaded and ready to run at the ....

....be loaded in a software scheduling queue. To allow a traditional RISC pipeline design, we assume a block multithreading model [23, 3] in which blocks of instructions are executed from each context in turn, rather than a cycle bycycle interleaving of instructions from the different contexts [20, 15, 13]. At any given time, the processor is executing one of the loaded threads. A context switch occurs when the processor switches from executing one loaded thread, to executing another loaded thread, an operation that can be done in 1 to 20 cycles, depending on the processor design. A thread swap ....

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JamesLaudon, AnoopGupta, and Mark Horowitz. Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations. In Proceedings of the Sixth International Conferenceon Architectural Support for Programming Languages and Operating Systems, pages 308--318. ACM Press, October 1994.

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