Anoop Gupta, John Hennessy, Kourosh Gharachorloo, Todd Mowry, and Wolf-Dietrich Weber. Comparative Evaluation of LatencyTolerating Techniques. In Proceedingsof the 18th Annual International Symposium on Computer Architecture, pages 254--263. ACM, May 1991. Home/Search Document Not in Database Summary Related Articles |
This paper is cited in the following contexts:
Thread Prioritization: A Thread Scheduling Mechanism for.. - Fiske, Dally (1995) (3 citations) (Correct)
....shared are simulated in detail. That is, it is assumed that all local instruction and data references (to a thread s stack for instance) hit in the cache. This assumption has been found to be a reasonable approximation of the case where every single memory reference is simulated through the cache [5, 9] since the hit rates for instructions and local data are typically very high. 3.2 System Parameters The basic system consists of a collection of multiplecontext processing nodes connected by a high speed interconnection network. Each processing node has a cache and some portionof the global ....
Anoop Gupta, John Hennessy, Kourosh Gharachorloo, Todd Mowry, and Wolf-Dietrich Weber. Comparative Evaluation of LatencyTolerating Techniques. In Proceedingsof the 18th Annual International Symposium on Computer Architecture, pages 254--263. ACM, May 1991.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC