J. Cong. An Interconnect-Centric Design Flow for Nanometer Technologies. In Proc. of the IEEE, vol. 89, No. 4, pp. 505-528, April 2001.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....4, for realistic as well as ideal copper resistivity. The global signal wire repeaters are found to be as high as 5.5 million at the 50 nm technology node with reasonable copper resistivity and a Rent s exponent of 0.55. We compare our repeater number estimates with those obtained by other authors [4], 15] at the 70 nm technology node (Table 2) Our prediction of about 0.85 million repeaters, for a Rent s exponent of 0.55, lies between the two numbers predicted by references [15] and [4] where as, a Rent s exponent of 0.6 yields results which match well with [4] The repeater estimate ....

....a Rent s exponent of 0.55. We compare our repeater number estimates with those obtained by other authors [4] 15] at the 70 nm technology node (Table 2) Our prediction of about 0.85 million repeaters, for a Rent s exponent of 0. 55, lies between the two numbers predicted by references [15] and [4], where as, a Rent s exponent of 0.6 yields results which match well with [4] The repeater estimate obtained in [15] is quite less because in this work the global wires are kept at a constant pitch at future nodes. Table 2: Comparison of no. of repeaters of our approach with previous work. The ....

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J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of the IEEE, Vol. 89, No. 4, pp.

....the power delay metrics but also deteriorates the signal integrity due to capacitive and inductive crosstalk noises. Conventional approaches to interconnect synthesis aim at optimal interconnect structures in terms of interconnect topology, wire width and spacing, and buffer location and sizes [3]. In this paper, we study a signal encoding scheme to minimize coupling effects between interconnects. Signal encoding schemes have been proposed to minimize transition activities on buses while ignoring cross coupled capacitances. When statistical properties are unknown a priori, the bus invert ....

J. Cong. An Interconnect-centric design flow for nanometer technologies. In Int. Symp. VLSI Technology, Systems, and Applications, pages 54--57, June 1999.

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J. Cong. An Interconnect-Centric Design Flow for Nanometer Technologies. In Proc. of the IEEE, vol. 89, No. 4, pp. 505-528, April 2001.

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J. Cong, "An Interconnect-Centric Design Flow for Nanometer Technologies, " in Proceedings of IEEE, pp. 505--527, April 2001.

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J. Cong. An interconnect-centric design flow for nanometer technologies. Proceedings of the IEEE, 89(4):505--528, 2001.

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J. Cong, "An interconnect-centric design flow for nanometer technologies, " Proc. IEEE, vol. 89, pp. 505--528, Apr. 2001.

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J. Cong. An interconnect-centric design flow for nanometer technologies. Proceedings of the IEEE, 89(4):505--527, April 2001.

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CONG,J. 2001. An interconnect-centric design flow for nanometer technologies. Proc. IEEE 89,4 (Apr.), 505--527.

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J. Cong, "An interconnect-centric design flow for nanometer technologies, " in Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, pp. 54--57, June, 1999.

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J. Cong. An interconnect-centric design flow for nanometer technologies. In Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, pages 54-- 57, 1999.

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J. Cong, "An Interconnect-Centric Design Flow for Nanometer Technologies, " Proceedings of the IEEE, vol.89, issue 4, pp.505--528, April 2001.

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J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of the IEEE, vol. 89, pp. 505--527, April 2001.

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J. Cong. An interconnect-centric design flow for nanometer technologies. Proceedings of the IEEE, 89(4):505--527, April 2001.

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J. Cong, "An interconnect-centric design flow for nanometer technologies, " Proc. IEEE, vol. 89, pp. 505--528, Apr. 2001.

....[1] complicating layout and routing. Also, as the clock speed of the processor continues to increase correspondingly dropping the cycle time of the processor, the interconnect scaling problem becomes even more severe and the processor may be unable to communicate across the chip in a single cycle [1, 2]. Agarwal et al. 1] predict that current processor designs will improve by at best, 12.5 per year in terms of performance over the next fourteen years due to hardware scaling concerns. Prior work [1, 3, 4] has demonstrated the need to consider both cycle time and throughput (IPC) when measuring ....

J. Cong, "An interconnect-centric design flow for nanometer technologies," in Proceedings of IEEE, pp. 505--527, April 2001.

....deep sub micron 1. INTRODUCTION The International Technology Roadmap for Semiconductors (ITRS 2002 update) 18] predicts that there will be over ten billion transistors integrated on a single chip with an on chip local clock frequency of 28GHz in the 22nm technology by 2016. It was shown in [3] that even with the use of new interconnect materials and aggressive interconnect optimization, the delay of a 2cm global Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for ....

J. Cong. An interconnect-centric design flow for nanometer technologies. In Proceedings of the IEEE, pages 505--527, April 2001.

....global router. Index Terms Congestion, deep submicrometer, interconnect, physical hierarchy, placement, routing. I. INTRODUCTION I NTERCONNECT has become the dominating factor in determining overall system performance and reliability. Inevitably, it impacts all stages of the design flow. In [1], a three phase interconnect centric design flow was proposed. It includes: 1) interconnect planning; 2) interconnect synthesis; and 3) interconnect layout in order to emphasize interconnect planning and optimization throughout the entire design process. The interconnect planning phase is ....

....hierarchy of the design which reflects the logical dependency and relationship of various functions and components in the design. Such a logical hierarchy may not map well to a two dimensional layout solution, as it is usually conceived with little or no consideration of the layout information [1]. Therefore, in our interconnect planning stage, we first flatten the circuits in the logical hierarchy to the extent that we are certain about the physical locality (i.e. we are certain that the circuits in a module should physically stay together) We then generate a physical hierarchy to ....

J. Cong, "An interconnect-centric design flow for nanometer technologies, " Proc. IEEE, vol. 89, pp. 505--527, Apr. 2001.

....together with macros for area and wirelength minimization. Finally, the cells in each block are placed separately. Though this method can reduce the problem size to the extent where the floorplanning technique can be applied, the quality of the final placement may not be good. As pointed out in [8], pre partitioning standard cells to form rectangular blocks may prevent such a hierarchical method from finding an optimal or near optimal solution in It was derived from ISPD 98 (IBM) circuit benchmarks [4] for mixed macro and standard cell placement. We categorize placeable objects into ....

....and standard cell placement. We categorize placeable objects into big and small objects based on the assumption that the size difference between large and small objects should be greater than 20 or 30. terms of wirelength and delay minimization. Therefore, a new methodology was proposed in [8], which first flattens the logical hierarchy to the extent that we are certain that the circuit elements in each module of the flattened hierarchy should physically stay together. Then a physical hierarchy is generated, which defines the global, semi global, and local interconnects (based on ....

J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of the IEEE, vol. 89, pp. 505--527, April 2001.

....of interconnects becomes critical in determining system performance, reliability, and power. This requires early interconnect estimation, which has been difficult in the conventional logic centric design flow. To overcome this difficulty, an interconnect centric design flow has been proposed [1], in which the interconnect topology and geometry is determined at early design stages. This makes it possible to estimate interconnect delay, noise, and power at the early design stages, provided we have accurate interconnect models. For interconnect power modeling, the model has been commonly ....

....energy , where is the load capacitance and is the supply voltage. Although this model is simple and easy to deal with, it is not accurate in the deep submicron design. Fig. 1 shows that the error of the model becomes large for long interconnects under the 70 nm technology derived from NTRS 97 [1], 2] The error is due to the following coupling effects. Manuscript received October 9, 2001. This work was supported in part by the National Science Foundation under Award CCR 0096383. This paper was presented in part at the 36th Design Automation Conference, New Orleans, LA, 1999. This paper ....

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J. Cong, "An interconnect-centric design flow for nanometer technologies, " Proc. IEEE, vol. 89, pp. 505--528, Apr. 2001.

....1.6 billion, with a clock frequency of 28.7 GHz by the year 2016. Such high complexity poses significant challenges to the scalability of placement algorithms. The traditional way to handle large designs is through partitioning according to the logical hierarchy. However, it is pointed out in [7] that these hierarchies are derived with little or no consideration for the physical layout and they may not embed well in a twodimensional silicon surface. Therefore, it is proposed in [7] that the right way to partition the design is to first flatten the logic hierarchy to the extent that we are ....

....large designs is through partitioning according to the logical hierarchy. However, it is pointed out in [7] that these hierarchies are derived with little or no consideration for the physical layout and they may not embed well in a twodimensional silicon surface. Therefore, it is proposed in [7] that the right way to partition the design is to first flatten the logic hierarchy to the extent that we are certain about the physical locality of each module in the flattened design, and then construct a physical hierarchy (coarse placement) on this almost flattened netlist. The algorithm ....

J. Cong, "An Interconnect-Centric Design Flow for Nanometer Technologies," Proceedings of the IEEE, Vol. 89, No. 4, pp 505-528, 2001.

....Performance Keywords Placement, routing, congestion, interconnect, physical hierarchy, deep sub micron 1. INTRODUCTION Interconnect has become the dominating factor in determining overall system performance and reliability. Inevitably, it impacts all stages of the design flow. In [1], Cong proposed a three phase interconnect centric design flow, including (1) interconnect planning, 2) interconnect synthesis, and (3) interconnect layout in or # UCLA Computer Science Department, Los Angeles, CA 90095, Email: cchang, cong, yuanxin cs.ucla.edu IBM T.J. Waston Research ....

J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of the IEEE, vol. 89, pp. 505--527, April 2001.

....most likely that these buffers will be distributed rather randomly over the entire chip, which will definitely complicate global detailed routing and power ground distribution. To effectively address the above issues, as part of our general effort of developing an interconnect centric design flow [17], 8] we study in this paper the buffer block planning (BBP) problem, which automatically generates buffer blocks for interconnect optimization during physical level floorplanning. It considers buffer location constraints (e.g. hard IP blocks and predesign layout) and provides more regular ....

J. Cong, "An interconnect-centric design flow for nanometer technologies, " in Proc. Int. Symp. VLSI Technology, Systems, and Applications, Taiwan, June 1999, pp. 54--57.

....m technology with a 5 GHz clock as predicted in NTRS 97 [2] Optimal buffer insertion and wire sizing are performed using the TRIO package [3] with the driver, buffer, and receiver sizes being 100x the minimum size inverter. Device and interconnect parameters are based on those presented in [4]. 15.04 24.9 (mm) 0 7.5 22.5 4 clock 7 clock 6 clock 1 clock 2 clock decade, it has also been applied to other areas, such as image processing, combinatorial optimization, control theory, statistical mechanics, quantum electrodynamics, and linear algebra. Multilevel techniques for VLSI ....

Cong, J. An Interconnect-centric Design Flow for Nanometer Technologies, in Proceedings of the IEEE, vol. 89, 505-527, April 2001.

....architectures. Index Terms Interconnect optimization, wire planning, wire sizing. I. INTRODUCTION F OR deep submicron (DSM) very large scale integration (VLSI) designs, interconnect has become a dominant factor in determining the overall circuit performance, reliability, and cost [1] [4]. As a result, many interconnect optimization techniques have been proposed in recent years for interconnect performance optimization. Among these techniques, wire sizing optimization is to find proper wire width tapering or sizing function for an interconnect so that a certain objective function, ....

....and planned (usually two width design is adequate for both delay and area optimization) These predetermined wire widths for each layer will be used to plan and allocate proper routing resources, perform interconnect layout optimization, and generate final layouts. The reader may refer to [4] for more detailed discussions of how our wire width planning results can be used in an interconnect centric design flow. B. Effectiveness of Wire Width Planning In this section, the results from using 1 width and 2 width designs are presented to show the effectiveness of wire width planning. ....

J. Cong, "An interconnect-centric design flow for nanometer technologies, " Proc. IEEE, vol. 89, pp. 505--528, Apr. 2001.

....interconnect layout of optimized interconnects with possibly complex geometries. 2 MAJOR STEPS COMPONENTS IN THE FLOW This section describes the major steps components in the interconnect centric design flow shown in Figure 3. A more detailed description of these modules are available from [1]. 2.1 Interconnect Optimization Interconnect optimization determines the optimal in terconnect structure of each net in terms of interconnect topology, wire width and spacing, buffer locations and sizes, etc. to meet the performance and signal reliability requirements. Interconnect ....

J. Cong, "An interconnect-centric design flow for nanometer technologies," Proceedings of the IEEE, vol. 89, no. 4, pp. 505528, 2001.

....optimizations. Our IPEMs have been successfully used in interconnect architecture planning [28] buffer block planning for interconnect driven floorplanning [46] and MARCO GSRC technology extrapolation system (GTX) 50] We plan to apply them throughout an interconnect centric design flow [51] to achieve better design convergence in the future. ACKNOWLEDGMENT The authors would like to thank Prof. M. D. F. Wong from the University of Texas, Austin, Dr. W. Donath, Dr. D. Kung, Dr. R. Puri and Dr. L. Stok from IBM, Dr. M. K. Mohan and Dr. P. Arunachalam from Intel, and Dr. W. Long from ....

J. Cong, "An interconnect-centric design flow for nanometer technologies, " in Proc. Int. Symp. VLSI Technology Systems Applications, June

.... Driven Multiway Partitioning Jason Cong and Sung Kyu Lim UCLA Department of Computer Science, Los Angeles, CA 90095 fcong,limskg cs.ucla.edu Abstract Under the interconnect centric design paradigm, partitioning is seen as the crucial step that defines the interconnect [1]. To meet the performance requirement of today s complex design, performance driven partitioners must consider the amount of interconnect induced by partitioning as well as its impact on performance. In this paper, we provide new performance driven formulation for cell move based top down multiway ....

....be directly linked to interconnect in deep submicron geometries. Thus, addressing interconnect issues in all steps involved in VLSI design process has become an essential goal. Under the interconnectcentric design paradigm, partitioning is seen as the crucial step that defines the interconnect [1]. To meet the performance requirement of today s complex design, performance driven partitioners must consider the amount as well as performance related quality of the interconnect induced by partitioning. Cutsize minimization helps to lower the possibility of critical paths crossing partition ....

J. Cong. An interconnect-centric design flow for nanometer technologies. In Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, pages 54--57, 1999.

....and runtime results. 1 Introduction The conventional objective of partitioning is to minimize the number of connections among the subcircuits. Under the new interconnect centric design paradigm, however, partitioning is seen as the crucial step that defines the local and global interconnects [2]. To meet the performance requirement of today s complex design, partitioners must consider the amount of interconnect induced by partitioning as well as its impact on performance. Cutsize minimization helps to lower the possibility of critical paths crossing partition boundary multiple times, ....

J. Cong. An interconnect-centric design flow for nanometer technologies. In Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, pages 54-- 57, 1999.

....most likely that these buffers will be distributed rather randomly over the entire chip, which will definitely complicate global detailed routing and power ground distribution. To effectively address the above issues, as part of our general effort of developing an interconnect centric design flow [15], we study in this paper the buffer block planning (BBP) problem, which automatically generates buffer blocks for interconnect optimization during physical level floorplanning. It considers buffer location constraints (e.g. hard IP blocks and pre design layout) and provides more regular ....

J. Cong, "An interconnect-centric design flow for nanometer technologies," in Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, pp. 54--57, June, 1999.

....in deep submicron geometries. Thus, addressing interconnect issues in all steps involv ed in VLSI design process has become another essential goal. Under the new interconnect centric design paradigm, partitioning is seen as the crucial step that defines the local and global interconnects [1] as illustrated in Figure 1. T o meet the performance requirementoftoday s complex design, partitioners m ust consider the amountofinterconnect induced by par This researc h is partially supported b y the MARCO DARPA Gigascale Silicon Researc h Cen ter (GSRC) and NSF Young Investigator Award ....

J. Cong. An interconnect-centric design flow for nanometer technologies. In Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, pages 54-- 57, 1999.

....most likely that these buffers will be distributed rather randomly over the entire chip, which will definitely complicate global detailed routing and power ground distribution. To effectively address the above issues, as part of our general effort of developing an interconnect centric design flow [15], we study in this paper the buffer block planning (BBP) problem, which automatically generates buffer blocks for interconnect optimization during physical level floorplanning. It considers buffer location constraints (e.g. hard IP blocks and pre design layout) and provides more regular buffer ....

J. Cong, "An interconnect-centric design flow for nanometer technologies, " in Proc. of Int'l Symp. on VLSI Technology, Systems, and Applications, pp. 54--57, June, 1999.

No context found.

Jason Cong, "An Interconnect-Centric Design Flow for Nanometer Technologies", Proceedings of the IEEE, 89(4):505-528, April 2001.

No context found.

Cong, J. An interconnect-centric design flow for nanometer technologies. Proc. IEEE, 89(4), Apr. 2001. 505-528.

No context found.

J. Cong, "An interconnect-centric design flow for nanometer technologies, " Proc. IEEE, vol. 89, no. 4, pp. 505--528, Apr. 2001.

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