USAMI, K., IGARASHI, M., MINAMI, F., ISHIKAWA, T., KANAZAWA, M., ICHIDA, M., AND NOGAMI, K. 1998. Automated low-power technique exploiting multiple supply voltages applied to a media processor. J. Solid-State Circ. 33, 3, 463--472. Home/Search Document Not in Database Summary Related Articles Check |
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Power Minimization under QoS Constraints - Jennifer Wong Gangqu (2002) (Correct)
....in the last decade low power research has attracted a great deal of attention. Both power modeling and optimization have been addressed on many levels of the synthesis process [12] More recently, a number of researchers proposed the use of multiple voltages in order to reduce power consumption [5, 13, 16]. Furthermore, several variable voltage techniques have been reported [4, 8, 17] Also, several industrial multiple voltage low power designs have been reported. The common denominator in all the efforts has been that the operations on the critical path are scheduled at higher voltage and ....
K. Usami, M. Igarashi, F. Minami, T. Ishikawa, et. al. Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE Journal of Solid-State Circuits, vol.33, no.3, pp. 463-472, 1998.
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....P N sizing if advantageous. 2.4 Multiple Vaa Multiple supply voltages on a chip will be one of the most valuable tools for designers to fight the rise of dynamic power in nanometer design. Only a few designs based on this concept, all with relatively low clock speeds, have been reported [18,19]. However, results are promising, and the slow acceptance in high performance MPUs seems primarily due to a lack of urgency in dynamic power reduction. The general idea most often applied is that of clustered voltage scal ing (CVS) 20] With two V levels (V,h and Vaa,0, the circuit is ....
....critical path delay. Similarly, path slack distributions for highend MPUs show that over half of all timing paths commonly use less than half the clock cycle [21,22] Using Vdo, 0.65 Vad,h, this yields a 45 50 dynamic power reduction, considering 8 10 additional level conversion power. In [18], area overhead due to constrained cell placement, level converters, and added power grid routing was found to be 15 . The impact of post synthesis transistor re sizing on multiV processes is discussed in Section 3.3. The key challenges to the use of multiple supplies on a chip lie in minimizing ....
K. Usami, et al., "Automated low-power technique exploiting multiple supply voltages applied to a media processor," IEEE J. Solid-State Circ., pp. 463-472, Mar. 1998.
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....techniques have been proposed to combat this increase in leakage power. These approaches can be divided into two categories. The first category focuses on the static design time selection of slow transistors on non critical paths. These techniques include: conventional transistor sizing, lower Vdd [8, 10], stacked gates [14, 24, 21] longer channels [7] higher threshold voltages [20, 9, 19, 23, 1] and thicker ### ; we collectively refer to these as statically selected slow transistors (SSSTs) Once SSST techniques have been applied, most leakage current is concentrated on critical paths. For ....
K. Usami et al. Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE JSSC, 33(3):463--471, March 1998.
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....multiple supply voltages. Among them are constrained physical design problems and the resulting area delay power penalty due to level converters (LCs) which are required at the interface of different voltages. In contrast, these issues can be eased if only two supply voltages are used [2] 3] [5], 15] 26] In [3] for example, a layout scheme using two voltages is discussed together with its application to a media processor chip design. In [15] dual supply voltages were used successfully to design a chip of MPEG4 codec core at Toshiba Corporation. These show the feasibility of ....
....to operate at only after all its transitive fanouts have been selected to do so. Thus, some part of the circuit with high slack may be left to operate unnecessarily at , limiting the potential of further power reduction. To avoid this problem, an extended CVS structure was first proposed in [5] using the so called level sort technique and was improved recently in [18] In this structure, gates may be scattered among the gates. However, because of lack of a global view, the method may not be effective especially when the given timing constraints are tight. In addition, these techniques ....
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....applications in low level synthesis and optimization such as gate resizing for area power reduction, generation of performance constraints for module placement and routing, and twovoltage techniques for low power design. Here we show its application to low power design using dual supply voltages [4,5]. We can prove that the gain function for this purpose is given by e e = v d v E v C g v (the detailed derivation can be available by contacting authors) Usami first proposed a dual voltage approach based on the so called Cluster Voltage Scaling (CVS) 4] The basic idea ....
K. Usami, et al, "Automated Low Power Technique Exploiting Multiple Supply Voltage Applied to a Media Processor", Custom Integrated Circuit Conference, pp.131-134, 1997.
Provably Good Algorithm for Low Power Consumption with Dual.. - Chen, Sarrafzadeh (1999) (1 citation) (Correct)
....supply voltage (V ddl ) without violating the timing constraints. The disadvantage is that some part of the circuit with high slack may be left to operate unnecessarily at high supply voltage (V ddh ) limiting the potential of further power reduction. An extended CVS structure was introduced in [7] where gates of the same voltage may be located in different clusters. However, because of lack of global view, the algorithm easily gets trapped in a local minimum. Also, existing approaches did not account for the switching activity in the circuit. Since different value of two supply voltages ....
K. Usami, et al, "Automated Low Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor," Proc. of Custom Integrated Circuit Conf., pp.131-134, 1997.
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.... by voltage scaling without degrading the entire performance: The first is a technique in which supply voltage is globally scaled with scaling threshold voltage Vth, such as VTCMOS [2] The second is a DualV DD approach in which the reduced V DD is selectively applied to non critical paths [5][6]. The third is a variable supply voltage (VS) scheme in which V DD is controlled adaptively using an on chip DC DC converter [3] However, there have been few papers which present a methodology of making these techniques work together and show the level of power reduction we could reach. In this ....
....supply voltages are used. The reduced voltage (VDDL) is applied to the circuit on non critical paths, while the original voltage (VDDH) is applied to the circuit on critical paths. So far, a Clustered Voltage Scaling (CVS) technique [5] and an Extended Clustered Voltage Scaling (ECVS) technique [6] have been reported as Dual V DD approaches. These techniques do not change the critical path delay, resulting in keeping the entire circuit performance. The Dual V DD 35 th Design Automation Conference Copyright 1998 ACM 1 58113 049 x 98 0006 3.50 DAC98 06 98 San Francisco, CA USA ....
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Usami, K., et al., "Automated Low-power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor", IEEE CICC-97, pp.131-134, May 1997.
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