G. B. Adams, D. P. Agrawal, and H. J. Siegel. "A Survey and Comparison of Fault-Tolerant Multistage InterconnectionNetwork". Computer, pp.14--2" June 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... of semiconductor memories has been thoroughly studied, and a survey can be found in [89] while the theory of error detecting and correcting codes is reviewed in [76] The fault tolerant issues of the interconnection networks used to integrate processors and memory modules are discussed in [2]. Fault tolerance of systolic arrays a particular class of parallel machines has been studied to some extent, and some of the achievements in that area are surveyed in [1] All these areas are extremely important for dependable massively parallel computing. In this work we address the ....

....networks is given by Almasi and Gottlieb in [6, Chapter 8] Theoretical foundations for such networks are summarized by Pippenger in [83] The networks are made more reliable by employing redundancy. A survey of fault tolerant interconnection networks is presented by Adams et al. in [2]. An interesting interconnection network routing strategy was described by Preparata [85] in which fast routing is achieved by allowing for some messages to be lost and using a redundancy scheme [84, 86] to reconstruct lost information. The area of fault tolerance and efficiency of ....

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G. B. Adams III, D. P. Agrawal, H. J. Seigel, "A Survey and Comparison of Faulttolerant Multistage Interconnection Networks", IEEE Computer, 20, 6, pp. 14-29, 1987.

....Fig. 2 Tandem Banyan Switching Fabrics The bandwidth is expected to be improved, while the latency is stretched. The 16 input 16 output TBSF is used in a real multiprocessor, and the performance is evaluated[15] 3. 2 Fault recovery mechanism for the TBSF A large number of fault tolerant MINs [18] [21] 20] 22] 23] have been proposed and discussed. These MINs require the extra stages or links for fault recovery, and some of them provide independent multiple paths in the MIN[24] 20] like MIN with multiple outlets treat FUNAHASHI et al.: FAULT TOLERANCE OF THE TBSF AND PBSF 3 ed here. The ....

G.B.Adams III, D.P.Agrawal, H.J.Siegel, "A Survey and Comparison of Fault Tolerant Multistage Interconnection Networks," IEEE Computer Vol.20, pp.14-27, (Jun. 1987).

....is optimally fault tolerant if and only if the mask vectors of every n consecutive stages span the n dimensional vector space. 1 Introduction Multistage Interconnection Networks (MINs) enjoyed important applications in fields such as telecommunications and parallel computing in the past decades [1] [3] 9] 11] 12] They are widely used to construct interconnects in parallel computers as well as various network switches including ATM switches. One of the advantages of MINs is their ability to allow novel ways to tolerate component faults. In this paper, we focus our interest on the ....

G. Adams, D. Agrawal and H. Siefel, "A Survey and Comparison of Fault-Tolerant Multistage Interconnection Networks", IEEE Computer, pp. 14-27, June 1987.

....vertical direction, where an appropriate labelling scheme enables to calculate, whether the message should be sent east or west in horizontal moves, and north or south in vertical moves respectively. Banyan Hypercube BQ(h;n; s) Yous 90] A Banyan network is a multistage interconnection network [Adam 87] its topology is a directed graph with a unique path from every base to every apex 28 where normally the bases and apexis represent processors or memory modules, whereas all other nodes are switching cells (see [Goke 73] or [Sieg 79] for a more detailed discussion of Banyan networks) In a ....

G. B. Adams, D. P. Agrawal, and H. J. Siegel. "A Survey and Comparison of Fault-Tolerant Multistage Interconnection Network". Computer, pp. 14--27, June 1987.

....of the inputs and outputs for routing, and 5. papers that explore the problem of testing a network for faults. Some of the earliest papers in these five categories are [23] 2, 3, 22, 30] 29] 5, 9] and [22] respectively. This paper falls into categories three and four. For a survey, see [1]. More recently, Varma [34] suggested that packets can avoid faults and still reach their destinations by first routing to an intermediate destination. Leighton, Maggs, and Sitaraman [15] proved that even if an adversary is allowed to place Theta(N= log N ) worstcase faults in an N node butterfly ....

G. B. Adams, III, D. P. Agrawal, and H. J. Siegel. A survey and comparison of fault-tolerant multistage interconnection networks. Computer, 20:14--27, June 1987.

.... combining interconnection network that is well suited for implementing synchronous concurrent reads and writes is studied in [27] the combining properties are used in their simplest form only to implement concurrent access to memory) The network can be made more reliable by employing redundancy [1]. With this architecture, our algorithmic techniques become applicable; i.e. the algorithms and simulations we develop will work correctly, and within the claimed complexity bounds (under the uniform cost memory access assumption) when the underlying components are subject to the failures within ....

....locations within the progress tree d. Each processor uses some constant amount of private memory to perform simple arithmetic computations. An important private constant is PID, containing the initial processor identifier. 4 ALGORITHMS FOR THE WRITE ALL PROBLEM 17 0 1 2 3 4 5 6 [7] 0] [1] [4] 6] C C CO C C CW ffl C C CW C C CO Delta Delta Delta Delta Delta Delta A A AU j j j Q Q Q A A AK s s s s s s s Figure 3: Processor traversal of the progress tree. Thus, the overall memory used is O(N P ) and the data structures are simple. Control flow: The algorithm ....

G. B. Adams III, D. P. Agrawal, H. J. Seigel, "A Survey and Comparison of Fault-tolerant Multistage Interconnection Networks", IEEE Computer, 20, 6, pp. 14-29, 1987.

.... tolerance using replication and coding techniques [31] Processors and memory are interconnected via a synchronous network [33] A combining interconnection network well suited for implementing synchronous concurrent reads and writes is in [23] and can be made more reliable by employing redundancy [2]. 2.2 Measures of Efficiency We use a generalization of the standard Parallel time ThetaProcessors product to measure work of an algorithm when the number of processors performing work fluctuates due to failures or delays [15, 16] In the measure we account for the available processor steps and ....

G. B. Adams III, D. P. Agrawal, H. J. Seigel, "A Survey and Comparison of Faulttolerant Multistage Interconnection Networks", IEEE Computer, 20, 6, pp. 14-29, 1987.

....same fan in. The resulting network is of type IBC k if the new stage implements the cube k function, for some 0 k n Gamma 1. See, for example, Figure 5.1a. Variations of this type of networks have been studied in the context of designing fault tolerant networks (see, for example, the survey in [1]) Thus, any possible IBC network has exactly two paths from any input x to any output y. By convention, a type 0 path (denoted P 0 , and used subsequently with additional subscripts) leaves the extra stage from an upper output port, and a type 1 path (denoted, P 1 ) leaves from a lower ....

....Proof of 2: We first outline a simple polynomial time algorithm that accepts the problem instance if there exists a feasible solution, and rejects, otherwise (the algorithm is not optimized for running time, rather its structure simplifies the proof) 0] set L = f(s; t) q(s; t) 1g. [1] For each demand q(s; t) 1, allocate all essential edges P 0 s;t P 1 s;t to the demand. If any such edge has been previously allocated then reject. 2] Repeat until no more demands can be removed from the current set L: for each demand (s; t) 2 L, examine each edge e 2 P 0 s;t [ P 1 s;t ....

[Article contains additional citation context not shown here]

G. Adams III, D. Agrawal, and H. Siegel, A survey and comparison of fault-tolerant multistage interconnection networks, Computer, 20 (1987), pp. 14--27.

.... combining interconnection network that is well suited for implementing synchronous concurrent reads and writes is studied in [26] the combining properties are used in their simplest form only to implement concurrent access to memory) The network can be made more reliable by employing redundancy [2]. 2.2 Measures of Efficiency The complexity measure used throughout this work is the available processor steps of [21] It generalizes the fault free Parallel time ThetaProcessors product and accounts for all steps performed by the active processors. Definition 2.1 Consider a computation with ....

G.B. Adams III, D.P. Agrawal and H.J. Seigel, A Survey and Comparison of Fault-tolerant Multistage Interconnection Networks, IEEE Computer 20 6 (1987) 14--29.

....can be obtained from the switch node table of Figure 7. All other modeling methodology remains the same. The proposed availability model is aimed basically at unique path MINs. The analysis, within a limited scope, can be used for fault tolerant multipath MINs. A survey of such MINs is reported in [2]. Fault tolerance can be improved by using various techniques. These techniques include addition of extra stages, increasing the number of ports, replicating the MIN, crosslinking, bypassing, etc. 2] As the redundancy and topology of the fault tolerant MINs vary, it is not possible to formalize a ....

....limited scope, can be used for fault tolerant multipath MINs. A survey of such MINs is reported in [2] Fault tolerance can be improved by using various techniques. These techniques include addition of extra stages, increasing the number of ports, replicating the MIN, crosslinking, bypassing, etc. [2]. As the redundancy and topology of the fault tolerant MINs vary, it is not possible to formalize a general technique for computing availability. The modelling technique for the PE subsystem and the MM subsystem however remains the same in all cases. Modelling of the MIN subsystem would vary with ....

G. B. Adams, D. P. Agrawal, and H. J. Siegel, "A Survey and Comparison of FaultTolerant Multistage Interconnection Networks," IEEE Computer, pp. 14-27, June 1987.

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G. B. Adams, D. P. Agrawal, and H. J. Siegel. "A Survey and Comparison of Fault-Tolerant Multistage InterconnectionNetwork". Computer, pp.14--2" June 1987.

No context found.

G.B. Adams III, D.P. Agrawal, and H.J. Siegel, "A Survey and Comparison of Fault-Tolerant Multistage Interconnection Networks, " Computer, June 1987, pp. 14--27.

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ADAM87: Adams, George B. III, Agrawal Dharma P., and Siegel, Howard J., "A Survey and Comparison of Fault-Tolerant Multistage Interconnection Networks", IEEE Computer, June 1987.

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