A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, X. Ji, "Adapting Cache Line Size to Application Behavior", Int'l Conf. Supercomputing, 1999, pp. 145154.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....[24] 18] 61] 37] We can also consider static approaches. The amount of spatial locality is analyzed at compile time. In this method, loop structures inherent in programs will be exploited. Special instructions are inserted in program codes by compiler in order to change the cache line size [60], 61] 3.2.5 Optimizing Data Placement Conflict misses take place when two data compete for a cache location. If we can re allocate one of the competing data address, the conflict miss can be avoided. Data placement optimization is a static approach to reducing the conflict misses [58] 44] ....

A. V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji,"Adapting Cache Line Size to Application Behavior," The International Conference on SuperComputing,Nov. 1999.

....for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and or a fee. CODES 2000 San Diego CAUSA Copyright ACM 2000 158113 268 9 00 5. 5.00 be one of the only ways tomorrow huge capacity chips can actually be utilized. Applications, especially those representing embedded systems, differ greatly in terms of their power, performance and size requirements. Though using the same basic architecture, applications may ....

....could vary from 8 to 32 bits. The buses could have used more powerful encoding, such as TO for address [1] or limited weight codes for data [9] We could have used code compression. Furthermore, a parameter aware compiler could be used to optimize an application for a particular configuration [13] These possibilities imply that we may be able achieve tradeoffs with ranges of 100x or even 1000x, making parameterized systems widely applicable and hence making further focus on parameterized system design important. 101 8. ....

A.V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, X. li. Adapting Cache Line Size to Application Behavior. International Conference on Supcrenmputing, 1999.

....A number of proposals have been made for adaptive configurable hardware mechanisms targeted at performance and or power optimization. A few important examples follow. Configurable caches and TLBs line sizes and associativity are adjusted in response to pro gram referencing behavior [2, 3]. Allocation of memory hierarchy resources cache memory resources are divided among levels in the cache hierarchy [4] or configured for other uses, e.g. instruction reuse [5] Allocation of memory buffer resources the same buffer resources are used for stream buffers or victim buffers, ....

.... cache memory resources are divided among levels in the cache hierarchy [4] or configured for other uses, e.g. instruction reuse [5] Allocation of memory buffer resources the same buffer resources are used for stream buffers or victim buffers, depending the current needs of the program [3]. Configurable branch predictors the length of the global history register [6] in a gshare (or related) predictor is varied. Configurable instruction windows sections of the issue window are disabled when there is low instruction level parallelism [7, 8] Configurable pipelines ....

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau and X. Ji, "Adapting Cache Line Size to Application Behavior," Intl. Conf. on Supercomputing, July 1999, pp. 145-154.

....as well. However, our reconfigurable cache organization is general enough to include other applications for the SRAM arrays including instruction reuse. Other reconfigurable approaches like the Impulse Project [20] the Galileo project [15] the Stream Memory Controller [78] and other studies [54, 125] also propose adaptive cache designs to address the problem of inefficient cache usage. However, these approaches primarily focus on application specific mechanisms to either (i) dynamically reorder memory accesses to exploit parallelism and locality, and or (ii) change cache organization, ....

Alexander V. Veidenbaum, Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, and Xiaomei Ji. Adapting Cache Line Size to Application Behavior. In Proceedings of the International Conference on Supercomputing, 1999.

....but may not give best Figure 2: The canonical application adaptive reconfigurable architecture, where elements of reconfigurable logic can in general be attached to all elements of interconnect, logic, and memory in the system. Page 10 of 37 performance on any particular application[3]. Similar constraints apply to other performance critical aspects such as value prediction, branch prediction, and data movement. In contrast, a processor incorporating reconfigurability can adopt optimal policies (and in some cases better mechanisms) for the application, enabling increased ....

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, X. Ji, Adapting Cache Line Size to Application Behavior. To appear in Proceedings of the 13 th ACM International Conference on Supercomputing, 1999(ICS '99).

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A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, X. Ji, "Adapting Cache Line Size to Application Behavior", Int'l Conf. Supercomputing, 1999, pp. 145154.

....cache sizes. Instead of this traditional cache architecture, we use a more flexible local memory, containing possibly multiple modules targeting different types of locality, to fine tune the balance between performance and power. Reconfigurable cache architectures have been proposed recently [29] to improve the cache behavior for general purpose processors, targeting a large set of applications. However, the extra control needed for adaptability and dynamic prediction of the access patterns results in a power overhead which is prohibitive in embedded systems. Instead, we statically target ....

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In ICS, 1999.

....hierarchy reconfiguration [1] dynamically detects application phase change and hit miss tolerance. Then the boundaries between different levels of memory hierarchy are adjusted to improve memory hierarchy performance while taking energy consumption into consideration. Adaptive cache line size [14] exploits changing application locality with different cache line size to improve performance. Pipeline gating [10] dynamically stalls instruction fetch to control rampant speculation in the pipeline. It reduces power consumption by reducing the number of wrong path instructions. 3. Dynamic ....

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In Int'l Conf. on Supercomputing, pages 145--154, 1999.

....Section 4 and Section 5. Cache performance and system performance are shown in Section 6. This report is concluded with future work in Section 7. 2 Related Work Previous research has investigated the exploitation of changing application locality for better cache performance and low traffic. In [16, 12], we have proposed to adapt cache line size based on the spatial locality where different cache lines can have different sizes. If two neighboring cache lines have neighboring tags, there is good spatial locality between these two lines. These lines can merge into a line of double size so that one ....

....for data with good spatial locality. The line size for a superload is four times the line size for a normal load. Two approaches for loads classification have been proposed, the offline profiling approach and the online prediction approach. The online approach is similar to our approach used in [16, 12] because the spatial locality among neighboring lines is predicted. However, our approach is simpler and can support multiple line sizes; while the online approach in [17] only supports two line sizes. In a sector cache [9, 13] a cache sector consists of several contiguous cache lines. All the ....

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In Int'l Conf. on Supercomputing, pages 145--154, 1999.

....wide range of cost performance power tradeo#s in the context of programmable embedded systems. III) In the domain of Computer Architecture, 9] 12] propose the use of hardware stream bu#ers to enhance the memory system performance. Reconfigurable cache architectures have been proposed recently [20] to improve the cache behavior for general purpose processors, targeting a large set of applications. However, the extra control needed for adaptability and dynamic prediction of the access patterns while acceptable in general purpose computing where performance is the main target may result in a ....

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In ICS, 1999.

....or with compiler assistance. A cache with a fixed large cache line is used in [10] in association with a predictor to only fetch the parts of the cache line that are likely to be used. Adaptive cache line size was shown to improve the miss rate without an appreciable increase in bandwidth in [18], 19] and [6] A scheme for adapting the cache line size dynamically was proposed in [18] A special adaptive controller is incorporated in the cache access controller to monitor the memory access pattern of an application and change the line size to double or half its original size at a time in ....

....association with a predictor to only fetch the parts of the cache line that are likely to be used. Adaptive cache line size was shown to improve the miss rate without an appreciable increase in bandwidth in [18] 19] and [6] A scheme for adapting the cache line size dynamically was proposed in [18]. A special adaptive controller is incorporated in the cache access controller to monitor the memory access pattern of an application and change the line size to double or half its original size at a time in order to suit the application s needs. In [18] the cache line is truly variable, whereas ....

[Article contains additional citation context not shown here]

Alexander V. Veidenbaum, Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, and Xiaomei Ji. Adapting cache line size to application behavior. In Proceedings ICS'99, June 1999.

....hardware adaptivity in the design of data cache. It is a part of a more general effort, the Adaptive Memory Reconfiguration and Management Project (AMRM) at the University of California Irvine, to apply adaptivity to the design of a memory hierarchy. More information about AMRM can be found in [2, 17]. There are several possible cache parameters that one can dynamically adapt. They include cache size, line size, write policy, write buffering, prefetching, etc. Some of these are only adaptable in theory. For instance, the cache size is largely determined by technology parameters and desired ....

....the cache line size. This paper introduces a cache design with a hardware adaptive line size. To our knowledge, such an organization has not been previously explored. Previous research [6, 12] has shown that different applications exhibit different spatial temporal localities. We have shown in [17] that different parts of an application also exhibit different spatial temporal localities. It will be ideal if a cache line size can be set per application or the size can be changed dynamically for different parts of an application. In reality, most processors support only one cache line size. ....

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In Int'l Conf. on Supercomputing, pages 145--154, 1999.

....architectural mechanisms, hardware assisted blocking, prefetching and dynamic cache structures that optimize movement and placement of application data through the memory hierarchy. For a description of the AMRM approach to architectural adaptation the reader is referred to [1] 2] [3]. The AMRM prototype board was designed to serve two purposes. It allows rapid prototyping of a variety of memory hierarchy architectures and adaptive caching mechanisms. Applications running on a host processor can be instrumented to use the board s memory hierarchy. Processor independence is ....

Alexander V. Veidenbaum et. al., Adapting Cache Line Size to Application Behavior,

....or with compiler assistance. A cache with a fixed large cache line is used in [10] in association with a predictor to only fetch the parts of the cache line that are likely to be used. Adaptive cache line size was shown to improve the miss rate without an appreciable increase in bandwidth in [18], 19] and [6] A scheme for adapting the cache line size dynamically was proposed in [18] A special adaptive controller is incorporated in the cache access controller to monitor the memory access pattern of an application and change the line size to double or half its original size at a time in ....

....association with a predictor to only fetch the parts of the cache line that are likely to be used. Adaptive cache line size was shown to improve the miss rate without an appreciable increase in bandwidth in [18] 19] and [6] A scheme for adapting the cache line size dynamically was proposed in [18]. A special adaptive controller is incorporated in the cache access controller to monitor the memory access pattern of an application and change the line size to double or half its original size at a time in order to suit the application s needs. In [18] the cache line is truly variable, whereas ....

[Article contains additional citation context not shown here]

Alexander V. Veidenbaum, Weiyu Tang, Rajesh Gupta, Alexandru Nicolau, and Xiaomei Ji. Adapting cache line size to application behavior. In Proceedings ICS'99, June 1999.

.... number moment of cache hits and misses, to estimate the performance of processormemory systems [1] to guide cache optimization decisions [25] to guide compiler directed prefetching [17] or more recently, to drive dynamic memory sub system reconfiguration in reconfigurable architectures [13] [24]. We use the cache locality analysis techniques presented in [17] 25] to recognize and isolate the cache misses in the compiler, and then schedule them to better hide the latency of the misses. III. Additional related work addresses extraction and utilization of accurate memory timing in the ....

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In ICS, 1999.

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Veidenbaum, A., Tang, W., Gupta, R., Nicolau, A., Ji, X. Adapting cache line size to application behavior. International Conference on Supercomputing, June 1999.

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VEIDENBAUM, A., TANG,W.,GUPTA, R., NICOLAU, A., AND JI,X. 1999. Adapting cache line size to application behavior. In International Conference on Supercomputing.

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VEIDENBAUM, A., TANG, W., GUPTA, R., NICOLAU, AND JI. X., 1999. Adapting cache line size to application behavior. In Proceedings of the 1999 International Conference on Supercomputing. ACM, New York, NY, USA, 145--154.

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Alexander V. Veidenbaum et al. Adapting cache line size to application behavior. In Proc. ICS '99, pages 145--154, 1999.

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A. V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting Cache Line Size to Application Behavior. In Proc. Int. Conf. on Supercomputing, pages 145--154, 1999.

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A. V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji, "Adapting Cache Line Size to Application Behavior," in Proc. Int. Conf. on Supercomputing, June 1999.

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A. V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji, "Adapting Cache Line Size to Application Behavior," in Proc. Int. Conf. on Supercomputing, June 1999.

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A. V. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji, "Adapting cache line size to application behavior," in Proc. Int. Conf. Supercomputing, pp. 145--154, June 1999.

No context found.

A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau and X. Ji, "Adapting Cache Line Size to Application Behavior," Intl. Conf. on Supercomputing, July 1999, pp. 145-154.

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A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau and X. Ji, "Adapting Cache Line Size to Application Behavior," Intl. Conf. on Supercomputing, July 1999, pp. 145-154.

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