G. Radin, "The 801 Minicomputer," IBM Journal of Research and Development, Vo.23, No.3, May 1983, pp.237--246.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....hits. In this example cache write generate is an improvement over write around and write allocate. 2.1 Related Work Improving cache write efficiency has been explored earlier in different forms in several systems. Many systems provide software control of cache write updating such as the IBM 801 [14], the LSI 4 Logic Sparc chip cache controller [10] and the Wisconsin Multicube [4] In these processors and protocols, there are special instructions to selectively update cache lines, avoiding reads. This control is only available in supervisor mode, and application programs cannot directly use ....

G. Radin, "The 801 Minicomputer," in Proceedings, Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, CA, March 1-3, 1982, pp. 39-47.

....rely on optimising compilers and large cache memories to maximise the use of registers and minimize references to main memory. The underlying principles of the RISC approach had already been laid down by IBM in their 801 computer, developed in late 1970s at IBM s Thomas J Watson Research Center [Radi83]; the first prototype VLSI RISC processors were developed in early 1980s at the University of California, Berkeley [Kate85] and at Stanford University [Henn81] Since then, and amidst an ever lasting controversy on the issue of system complexity [Whar92] Alli92] several commercial powerful RISC ....

Radin, G., "The 801 Minicomputer", IBM Journal of Research and Development, 27, 3, 1983, pp. 237-246.

....proposed to handle branches in pipelined processors. Table 1 lists three such methods. Delayed Branching has been a popular method to absorb branch delay in microsequencers of microprogrammed microengines. This technique has also been adopted by many recent processor architectures including IBM 801[37], Stanford MIPS[14] Berkeley RISC [33] HP Spectrum [3] SUN SPARC [43] MIPS R2000 [25] Motorola 88000[30] and AMD 29000[1] In this approach, instruction slots immediately after a branch are reserved as the delay slots for that branch. The number of delay slots has to be large enough to cover ....

G. Radin, "The 801 Minicomputer", Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, pp.39-47, March, 1982.

....become apparent that more parallelism must be exploited in order to keep increasing system performance. A wide variety of architectures have been proposed that attempt to exploit the parallelism available in application programs at different granularities [20] For example, pipelined processors [1, 11, 26] and multiple instruction issuing processors, such as the superscalar [11, 12, 32, 33] and VLIW [5, 8, 18] machines, exploit the fine grained parallelism available at the machine instruction level. In contrast, shared memory multiprocessors [9, 14, 24] typically exploit coarse grained parallelism ....

George Radin, "The 801 Minicomputer," IBM Journal of Research and Development, Vol. 27, No. 3, pp. 237-246, May 1983.

....and main memory refer to data using the same virtual address. The cache is not the primary home for this data, but must ensure that data is always saved out to memory to avoid inconsistency. Although some caches allow programs to avoid caching some data, or to explicitly allocate data in the cache [68], the program typically has no control over how memory operands are mapped into the cache. 2.2.2 NSF and memory hierarchy Figure 2 3 illustrates how the Named State Register File fits into the memory hierarchy. As with conventional register files, the NSF defines a register name space separate ....

....Conventional register files use a short index to select a register, while the NSF uses an expanded name space consisting of Context ID and offset. Cache lines are typically allocated and managed using a fixed hardware algorithm. Some data caches allow the program to explicitly allocate cache lines [68]. This allocation is only useful in writing new data spaces, since the compiler must guarantee that the entire cache line will be written, to avoid incorrectly allocating partial lines [46] Property Determines Data Cache Register File Named State File Latency Performance 1 cycle 1 cycle 1 ....

G. Radin. "The 801 minicomputer." Proceedings from the Symposium on Architectural Support for Programming Languages and Operating Systems, pages 39--47, March 1982.

....operate a UNIX variant, HP UX Version 6.5. This workstation serves as a traffic generator. Using such a workstation (with its circa 3 million instructions per second (MIPS) performance) is not as far fetched as it might at first seem, as (1) all RISC (reduced instruction set computer) technology [15, 16] workstations we are aware of operate UNIX or a variant; 2) operational distributed shared memories [12, 21] using UNIX as a base exist; and (3) our measurement methodology, described next, is speed independent. One potential flaw in the analysis is that RISC architectures have many registers and ....

G. Radin, "The 801 Minicomputer," ACM SIGARCH Computer Architecture News 10, pp. 39-47 (March 1982).

....of these mechanisms, experimentation is discouraged. However, despite these difficulties, we believe that better computer systems (both hardware and software) are possible if the architecture is designed to operate synergistically with the compiler. Examples of such systems include the IBM 801 [Rad82] and the MIPS [HJB82] processors. Their designs were influenced largely by the decision to make pervasive use of high level languages and powerful compilers. To effectively evaluate a proposed architecture, one should analyze measurements from typical programs that are to be executed by the ....

G. Radin, "The 801 Minicomputer", Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, CA, March 1982, 39-47.

.... a simplified instruction set so that a complete CPU design could be implemented on a single VLSI chip [104] On the other hand, Cocke and associates in the IBM 801 Project explored a simplified instruction set combined with compiler code generation strategies to obtain improved cost performance [107]. Thus RISC concepts emerged from the desire to pack the greatest functionality into a chip and the idea of making an astute division of function between hardware and software. As semiconductor technology advanced, yielding chips with higher component densities, the goal of RISC architecture has ....

George Radin, "The 801 minicomputer," in Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, California, pp. 39--47, March 1982.

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G. Radin, "The 801 Minicomputer," IBM Journal of Research and Development, Vo.23, No.3, May 1983, pp.237--246.

No context found.

George Radin, "The 801 Minicomputer", Symposium on Architectural Support for Programming Languages and Operating Systems, pp. 39-47, 1982.

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