Amos R. Omondi. Design of a high performance instruction pipeline. Computer Systems Science and Engineering, 6(1):13 29, January 1991.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....to switch contexts will be close to the depth of the pipeline, as the partially executed instructions from the switching context will need to be flushed from the pipeline. In attempt to reduce this switch cost, a few blocked architectures have been proposed which replicate the pipeline registers [18, 19]. With this pipeline register replication, the contextswitch cost could be a low as a single cycle (at least one cycle is needed to broadcast the switch decision to the entire chip for use by the TLB, pipeline forwarding logic, etc) Unfortunately, replicating the pipeline registers results in a ....

Amos R. Omondi. Design of a high performance instruction pipeline. Computer Systems Science and Engineering, 6(1):13 29, January 1991.

....explicitly switched contexts in response to each Dataflow token, potentially on every instruction. Monsoon used no general registers, but fetched operands from a large, high speed local storage. Monsoon compensated for the slower operand access time by using a very deep processor pipeline. Omondi [63] has proposed a memory accumulator processor to support multiple concurrent tasks. The machine fetched operands directly from the data cache. This organization also used a very deep processor pipeline to cope with long operand fetch latencies. 24 Introduction 1.5.2 Each of these machines ....

Amos R. Omondi. "Design of a high performance instruction pipeline." Computer Systems Science and Engineering, 6(1):13--29, January 1991.

....bits are analogous to a scoreboard except that the processor context switches rather than stalls when the issue condition for an instruction is not met. Omondi has also proposed using a cache in a multithreaded memory accumulator machine to resolve data dependencies and rename variable accesses [8]. 1.2 Multithreaded Processors A multithreaded processor [10, 3] partitions a single large register file among a small set of resident processes. This organization results in inefficient use of registers and imposes a high overhead on switching to a process not in the resident set. With large ....

Amos R. Omondi. Design of a high performance instruction pipeline. Computer Systems Science and Engineering, 6(1):13--29, January 1991.

....at a time. An alternative is to provide a context cache that holds register bindings for variables from several threads, thereby avoiding the need to explicitly save and restore register contexts. A related use of a cache memory to build an efficient instruction pipeline has been reported [100]. Another possibility is to identify interrupt points in the machine code where the contents of the register context would be guaranteed (by the programmer compiler) to have no effect on the future course of the process. At these points a switch between activities may be performed without the cost ....

Amos R. Omondi, "Design of a high performance instruction pipeline," Computer Systems Science and Engineering, 6(1):13--29, January 1991.

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