C. Lee, K. Chen and T. Mudge, "Instruction Prefetching using Branch Prediction Information," in Proc. Intl. Conf. on Computer Design: VLSI in Computers and Processors, 1997, pp. 593--601.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....engine, they were able to initiate data cache prefetches farther in advance than if they had used the normal PC to do the address prediction. This allowed them to mask more of the data cache miss penalty. Chen and Baer only looked at using the LA PC for data prefetching [9] Chen, Lee and Mudge [7] examined applying the approach of Chen and Baer to instruction prefetching. They examined adding a separate branch predictor to the normal processor; so the processor would have 2 branch predictors, one to guide prefetching and one to guide the fetch engine. The separate branch predictor uses a ....

I.K. Chen, C.C. Lee, and T.N. Mudge. Instruction prefetching using branch prediction information. In International Conference on Computer Design, pages 593--601, October 1997.

....can be kept on all previous successors to this block [Kim93] or the most recent successor ( target prefetch ) Hsu98] and prefetch these lines. Alternatively, a lookahead PC can use branch prediction to race ahead of the standard program counter, prefetching along the likely execution path [Chen94, Chen97]. However, information must be maintained to determine when the actual execution has diverged from the lookahead PC s path, and then restart the lookahead along the correct path. Unfortunately, many standard prefetching techniques are not appropriate for FPGA configurations. Data prefetching ....

I.-C. Chen, C.-C. Lee, T. Mudge, "Instruction Prefetching Using Branch Prediction Information", International Conference on Computer Design, pp. 593-601, 1997.

....code within a function, and the CGHC for prefetching across function calls. We show that CGP takes good advantage of the nextline prefetching scheme and also outperforms OM with a pure NL scheme by 7 . Researchers have proposed several techniques for nonsequential instruction prefetching [22, 7, 13, 17]. Of these, the work that is closest to CGP is that of Luk and Mowry [13] They proposed cooperative prefetching where the compiler inserts prefetch instructions to prefetch branch targets. Their approach, however, requires ISA extensions to add four new prefetch instructions: two to prefetch the ....

I.-C.K. Chen, C.-C. Lee, and T. Mudge. Instruction Prefetching Using Branch Prediction Information. In Proceedings of International Conference on Computer Design, pages 593--601, October 1997.

....and are easy to implement. Although they achieve good miss coverage, we show that the prefetches are not issued early enough to cover the access latency of the L2 cache. Moreover, these techniques do not attempt to cover miss penalties associated with taken branches. The non sequential techniques [4, 12, 15, 17] are closely tied to branch prediction. The objective of these techniques is to predict the addresses of instructions that will be executed after 1 or more branches, at least one of which is a taken branch. To predict prefetch addresses past 2 or more branches, these techniques rely on having a ....

....to predict data addresses to be prefetched. The LA PC is incremented and maintained in the same fashion as the PC with the help of its own dynamic branch predictor. Since the LA PC runs ahead of the regular PC, this technique in creases the prefetch distance. Branch Prediction Based Prefetching [4] applies the lookahead data prefetching technique [5] to instruction prefetching. It uses a separate branch predictor to trigger prefetches. The prefetch unit runs ahead, using a LA PC, and prefetches instructions based on its branch predictions which it logs. The execution unit checks the logs as ....

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I-C. K. Chen, C-C Lee, T. N. Mudge, "Instruction Prefetching Using Branch Prediction Information," Proceedings of the Int'l Conference on Computer Design, October 1997, pp. 593-601.

....of 21 30 , indicating substantial further room for improvement. The paper indicates that the relative performance of this approach will improve further over time, as the processor clock rate to memory latency gap grows, and as the number of cycles per instruction decreases. Chen et al. [Chen et al. 1997] propose another instruction prefetching method based on branch prediction. This method is based on their work done on data prefetching [Chen and Baer, 1995] which will be described in the next section) This scheme utilizes a small autonomous prefetching unit that speculatively traverses the ....

Chen, I., Chih-Chieh., L., and Mudge, T. (1997). Instruction prefetching using branch prediction information. In International conference on Computer Design, VLSI in Computers and Processors, pages 593--601.

....computing, i.e. execution performance is strictly limited by fetch performance. Efficient instruction cache performance is critical in order to keep the execution core satisfied. Instruction cache prefetching has been shown to be an effective technique for improving instruction fetch performance [2, 9, 6, 7, 13, 17, 18, 20, 21], and this is the focus of our paper. We recently proposed a scalable fetch architecture to relieve the fetch bottleneck [14] One aspect of that architecture was to decouple the branch predictor from the instruction cache. The branch predictor produces fetch blocks into a Fetch Target Queue ....

....in the presence of (2) and (3) above, the instruction cache does not have to be lockup free. 3. 2 Prior Cache Probe Filtering Research Prior instruction cache prefetch studies have examined filtering instruction prefetches based on whether or not the address was already in the instruction cache [2, 9]. For every instruction prefetch, these studies first check the instruction cache and only perform the prefetch if the block is not in the instruction cache. This assumes extra instruction cache ports to perform the cache probe check. In our simulations we examine the performance with and without ....

[Article contains additional citation context not shown here]

I.K. Chen, C.C. Lee, and T.N. Mudge. Instruction prefetching using branch prediction information. In International Conference on Computer Design, pages 593--601, October 1997.

....next two papers introduce and compare two simple yet effective 4 prefetching methods. The last one is a paper that studies prefetching along both paths of a branch instruction. 2.1 Branch Prediction based Instruction Prefetching 2.1. 1 Instruction Prefetching using Branch Prediction information [19] Instruction Prefetching can effectively reduce I cache misses and thus improve performance. In this paper, Mudge et al. employ a branch predictor and a small autonomous fetching unit which runs ahead of the execution unit to predict potentially useful instructions. They use a 4 issue machine with ....

I-C. K. Chen, L. C-C. Lee, T. Mudge. Instruction Prefetching Using Branch Prediction Information. International conference on Computer Design, VLSI in Computers and Processors, page 593 October 1997

No context found.

C. Lee, K. Chen and T. Mudge, "Instruction Prefetching using Branch Prediction Information," in Proc. Intl. Conf. on Computer Design: VLSI in Computers and Processors, 1997, pp. 593--601.

No context found.

I.K. Chen, C.C. Lee, and T.N. Mudge. Instruction prefetching using branch prediction information. In International Conference on Computer Design, pages 593--601, October 1997.

No context found.

I. Chen, C. Lee, and T. Mudge; "Instruction Prefetching Using Branch Prediction Information"; International Symposium on Microarchitecture, 1997.

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