| P. G. Emma, J. W. Knight, J. H. Pomerene, T. R. Puzak and R. N. Rechtschaffen, "Cache Miss Facility with Stored Sequences for Data Fetching", U.S. Patent 5,233,702(Issued: August 3, 1993). |
....experienced. An example of hardware based prefetching is the work by Chen and Baer [ChBa95] In this paper the authors propose keeping a history of the strides of data references, and using that information to make predictions as to what should be prefetched. IBM uses a similar hardware approach [EKPP93] in which they associate previous miss behavior with a load instruction and use that information to do prefetching. Among the most intriguing software approaches to reducing the miss penalty is a study by Abraham, et al. ASWR93] in which they observe that a very small number of load instructions ....
P. G. Emma, J. W. Knight, J. H. Pomerene, T. R. Puzak and R. N. Rechtschaffen, "Cache Miss Facility with Stored Sequences for Data Fetching", U.S. Patent 5,233,702(Issued: August 3, 1993).
....experienced. An example of hardware based prefetching is the work by Chen and Baer [ChBa95] In this paper the authors propose keeping a history of the strides of data references, and using that information to make predictions as to what should be prefetched. IBM uses a similar hardware approach [EKPP93] in which they associate previous miss behavior with a load instruction and use that information to do prefetching. A somewhat different hardware approach to reducing the miss penalty is put forth by [Joup90] The author makes the observation that a cache or a degree of associativity that is too ....
P. G. Emma, J. W. Knight, J. H. Pomerene, T. R. Puzak and R. N. Rechtschaffen, "Cache Miss Facility with Stored Sequences for Data Fetching", U.S. Patent 5,233,702(Issued: August 3, 1993). - 26 - # #
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