L. Gwennap, "Comparing RISC Microprocessors," Proceedings of the Microprocessor Forum, October 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....The amount of information stored in the two block ahead branch predictor is in the same range as in a conventional branch prediction mechanism. Moreover, any prediction scheme can be used to determine the outcome of conditional branches leading to better prediction accuracy. As described in [5], two different approaches are used to achieve high performance in superscalar machines: brainiacs vs. speed demons . The two block ahead predictor is really useful in double I fetch brainiac processors since it increases the amount of potential ILP. Furthermore, it can also be used effectively ....

L. Gwennap, "Comparing RISC Microprocessors," Proceedings of the Microprocessor Forum, October 1994.

.... represent two extremes of the microarchitectural spectrum, from complex brainiac CPUs that aggressively and dynamically reorder instructions to achieve a high IPC metric, to the clean, straightforward, and deeply pipelined speed demon CPUs that rely primarily on clock rate for high performance [48]. In addition to these realistic models, we examined a number of less realistic PowerPC based simulation models in order to explore the limits of performance obtainable with these new techniques. These models are described in the following sections. 2.1.1 PowerPC 620 The microarchitecture of the ....

.... represent two extremes of the microarchitectural spectrum, from complex brainiac CPUs that aggressively and dynamically reorder instructions to achieve a high IPC metric, to the clean, straightforward, and deeply pipelined speed demon CPUs that rely primarily on clock rate for high performance [48]. These machine models are described in detail in Section 2.1 on page 21. 3.4.1 PowerPC 620 620 LVP Unit Operation In the PowerPC 620 620 machine models, the LVP Unit predicts load values during dispatch, then forwards them speculatively to subsequent operations via the 620 s rename busses. ....

L. Gwennap. "Comparing RISC microprocessors." In Proceedings of the Microprocessor Forum, October 1994.

....branch predictors can use any of the branch prediction schemes to perform the very accurate predictions required to achieve high performance on superscalar processors. 1 Introduction Two different approaches are used in current processors to achieve high performance: brainiacs vs. speed demons [6]. While brainiacs favor the parallel execution of instructions and speed demons favor a high clock rate, both approaches are facing a similar difficulty with fetching instructions at a sufficient rate. The purpose of this paper is to propose a new branch pre This work was partially ....

L. Gwennap, "Comparing RISC Microprocessors," Proceedings of the Microprocessor Forum, October 1994.

.... 3 1 4 Complex FP 18 18 1 36 65 Branch(pred mispr) 1 0 1 1 0 4 Predict LCT LVPT Load PC Predicted CVU Cache Fetch Disp Ex1 Address Comp Actual Ex2 Address LVPT Index Verify Sample Address Load Execution Value Value Sample Store Execution that rely primarily on clock rate for high performance [Gwe94] The issue and result latencies for common instruction types on both machines are summarized in Table 5 . 4.1. The PowerPC 620 Machine Model The microarchitecture of the PowerPC 620 is summarized in Figure 4. Our model is based on published reports on the PowerPC 620 [DNS95, LTT95] and ....

Linley Gwennap. Comparing RISC microprocessors. In Proceedings of the Microprocessor Forum, October 1994.

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