I. Beer, S. Ben-David, C. Eisner, and A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool," DAC'96.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....1 and the SAT checker Grasp [11,12] without making use of features that are unique to either one of them. i We distinguish between the tool BM and the method BMC. We benchmarked the various optimizations, and also compared them to re suits achieved by RuleBase, IBM s BDD based Model Checker [1, 2]. RuleBase is considered one of the strongest verification tools on the market, and includes most of the reductions and BDD optimizations that have been published in recent years. The benchmark s database included 13 randomly selected reallife designs from IBM s internal benchmark set. ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. RuleBase: An industry oriented formal verification tool. In Proc. Design Automation Conference 96 (DAC96), 1996.

....the next state (second state on the path) F requires to be true sometime in the future (should be true on at least one state on the path) U means that holds until becomes true (there is some state on the path at which is true and on all preceding states is true) 2. 2 RuleBase RuleBase [1, 2] is an extension of the SMV model checker, developed by IBM. A model in RuleBase is specified in the Environment Description Language (EDL) which is a dialect of the SMV description language. RuleBase also allows verification of designs in traditional hardware description languages such as Verilog ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase: an Industry-Oriented Formal Verification Tool. In Proceedings of the 33rd Conference on Design Automation, pages 655-660, 1996.

....and efficient BDD representation as a buffer of bytes. This representation enables different variable orders in the sending and receiving processes. We implemented our technique on a loosely connected distributed environment of workstations, embedded it in a powerful model checker RuleBase [2], and tested it by performing reachability analysis on a set of large benchmark circuits. Compared to execution on a single machine with 512MB memory, the parallel execution on 32 machines with 512MB memory uses much less space, and reaches farther when the analysis eventually overflows. Our ....

....the BDD with its slice after reconstructing the BDD. 9 6 Experimental Results In this section we report initial performance results achieved using our approach. We implemented our partitioned BDD and embedded it in an enhanced version of McMillan s SMV [7] of the IBM Haifa Research Laboratory [2]. Our parallel testbed includes 32 RS6000 machines, each consisting of a 225MHz PowerPC processor and 512MB memory. The communication between the nodes consists of a 16Mbps token ring. The nodes are non dedicated; i.e. they are mostly workstations of employees who would often use them (and the ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase: an industry-oriented formal verification tool. In 33rd Design Automation Conference, pages 655--660, 1996.

....of current designs and the huge cost of delivering a faulty product [4] have led to a growing investment in functional verification and in the development of new technologies and methodologies in this area. This include sophisticated random test program generators [5] and model checking tools [6]. The design and implementation of software systems have strong similarities to the logic design and implementation of hardware systems. In both, the process starts with a high level design of the entire system, which is then broken into smaller units. Each unit is implemented and tested by ....

....system and verify that these properties hold. The main drawback in the use of model checking is the vast number of states that have to be examined and the complexity of the checked properties. Advances in model checking technology that improve the data structures used in symbolic model checking [6] and increase computing power have enabled model checking tools to handle more serious problems. Today model checking is a technology which the hardware industry not only uses, but also invests in heavily. Model checking is ideally suited for hardware verification, since hardware design is ....

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I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase: an industry-oriented formal verification tool. In Proceedings of the 33rd Design Automation Conference, pages 655--660, June 1996.

....the time several problems were identified in the control mechanism. The problems which were uncovered by the simulation environment were later analyzed and observed by the formal methods. RuleBase is a model checking based formal verification tool, developed by the IBM Haifa Research Laboratory [1]. It uses an enhanced version of SMV[3] as its verification engine. SMV is an efficient and robust symbolic model checker that uses binary decision diagrams (BDD) to represent the unit under test (UUT) The work described here provides brief technical overview of the MPEG elements which were used ....

I. Beer, S. Ben-David, C. Eisner, A. Landver, "RuleBase: An Industry-Oriented Formal Verification Tool", Proceedings of the design Automation Conference, DAC'96.

....under investigation. Therefore, it is essentially limited in its ability to provide deep insight into the model. In recent years, symbolic model checking and formal verification have been successfully used in the verification of communication protocols, as well as software and hardware systems [3]. Our work may be viewed as an extension of the recent research trend to bring together simulation based verification and formal verification. Some recent works, for example, have focused on improving the quality of simulation by using formal verification methods to generate test sequences that ....

....or to expand a counter example. A random choice is consistent with the counter example since all variables in the counter examples were chosen using the cone of influence reduction. Therefore, variables outside that cone cannot influence them. Such an inflator is part of the RuleBase package [3][26] We can improve the simple idea of observing the counter example by using the inflator. The counter example is inflated, using a set of variables mentioned in the coverability tasks. All the coverability tasks that are covered by the inflated trace are removed from the list. This reduces the ....

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I. Beer, S. Ben-David, C. Eisner, A. Landver. RuleBase: an Industry-Oriented Formal Verification Tool. Proc. DAC'96, pp. 655--660.

....invariance group automatically, once the symmetry group is given. Supplying the symmetry group usually requires only a high level understanding of the system and therefore is easier than supplying the invariance group. We implemented our methods within the enhanced model checking tool RuleBase [1], developed by the IBM Haifa Research Laboratories, and compared the performance of our methods with that of RuleBase. Our experiments show that our methods performed significantly better, with respect to both time and space, in checking liveness properties. For temporal safety properties they ....

....for computing Rep Theta S. Line 6 is implemented with the operator compose odd [14] which computes 9v ) using only two sets of BDD variables instead of three. 7 Experimental results We implemented the algorithms Hints Sym, Live Rep, and Create in the IBM s model checker RuleBase [1]. We ran it on a number of examples which contain symmetry. For each example we tuned our algorithms according to the evaluated formula, the difficulty level of computing the reachable states and the difficulty level of building the transition relation. In most cases, our algorithms outperformed ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. RuleBase: An industry-oriented formal verification tool. In Design Automation Conference, pages 655--660, June 1996.

....example, express properties of the temporal ordering of events without, in general, a regard for any quantitative measure on the elapsed time between the occurrences of the events. Real time temporal logics ( JM86] AH89] ACD90] EMSS92] and more generally quantitative logics ( BEH95] BEH95a] [BBEL96] [ET97] c.f. CCMMH94] cater for the expression of quantitative bounds on the occurrence of events. Such logics allow operators of the form AF P meaning that inevitably event P will occur within five time steps. The use of constants, 5 in this case, can be problematic, requiring detailed ....

....represented by transitions until the occurrence of an event. However, these logics cannot naturally express quantitative measures on the number of occurrences of independent events. We define and give model checking algorithms for General Parameterized CTL, GPCTL, c.f. JM86] BEH95] BEH95a] [BBEL96] [YMW97] ET97] which allows quantitative parameterization over the occurrence of events. For example, AF 3 Deltarequest response says that it is inevitable that a response will be issued before more than 4 occurrences of request. 9xAG(request ) AF x Deltarequest response) says that there is ....

Beer, I., Ben-David, S., Eisner, C. and Landver, A., RuleBase: an Industry-Oriented Formal Verification Tool. In 33rd Design Automation Conference, ACM, 1996.

....and CTL [10] for example, express properties of the temporal ordering of events without, in general, a regard for any quantitative measure on the elapsed time between the occurrences of the events. Real time temporal logics ( 17] 5] 2] 13] 14] and more generally quantitative logics ( 7] 8] [6] [15] c.f. 9] cater for the expression of quantitative bounds on the occurrence of events. Such logics allow operators of the form AF 5 P meaning that inevitably event P will occur within five time steps. The use of constants, 5 in this case, can be problematic, requiring detailed knowledge of ....

....of time units represented by transitions until the occurrence of an event. However, these logics cannot naturally express quantitative measures on the number of occurrences of independent events. We define and give model checking algorithms for General Parameterized CTL, GPCTL, c.f. 17] 7] 8] [6] [21] 15] which allows quantitative parameterization over the occurrence of events. For example, AF 3 Deltarequest response says that it is inevitable that a response will be issued before more than 4 occurrences of request. 9xAG(request ) AF x Deltarequest response) says that there is a ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase: an industry-oriented formal verification tool. In 33rd Design Automation Conference. ACM, 1996.

....range of behaviors. The accuracy and completeness of the system and specification models is a fundamental limitation for any formal method. The spectrum of formal methods for FDV is broad. At one end there are methods that are highly automated, but address only a very restricted problem space [Beer96, EET94, Goer97, Hard96, Kuel97, McMi93]. Methods at the opposite end, such as theorem proving, use formalisms to address a richer class of problems, and have mechanisms to use hierarchy and abstraction, but require a great amount of expertise to apply them [Cohn87, Cohn89, Owre96, Wind95] Simulation based design verification tries to ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. RuleBase: An industryoriented formal verification tool. In Proc. Design Automation Conf., pages 655--660, 1996.

.... model checking techniques, which provide a framework for reasoning about finite state systems [McM93] In recent years, Symbolic Model Checking, and formal verification in general, has been successfully used in the verification of communication protocols, as well as software and hardware systems [BBEL96]) Our work may be viewed as an extension of the recent research trend to bring together simulation based verification and formal verification. Some recent works, for example, have focused on improving the quality of simulation by using formal verification methods to generate test sequences that ....

....can be reached, we add an instrumentation that marks this line so it can be referred to by the rule. The model checker then checks the attainability of the marked line and CAT extracts and reports the answer. CAT uses RuleBase, a symbolic Model Checker developed by the IBM Haifa Research Lab ([BBEL96]) as its underlying engine. RuleBase can analyze models formulated in several hardware description languages, including VHDL and Verilog. The basis for CAT is RuleBases s Verilog parser, Koala. CAT parses the input Verilog de sign, extracts the information needed in the current coverability ....

I. Beer, S. Ben-David, C. Eisner, A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool", Proc. DAC'96, pp. 655--660.

....these interfaces, the methodology has to account for complex features such as instruction pipelines, pipeline interlocks, multiple instruction issue, multiple cycle instructions and speculative execution. Though formal verification tools have started gaining acceptance in the industry[8][9][10] 11] they do not provide a rigorous methodology for subsystem verification. Our verification methodology is able to bridge the wide gap between the abstract specification of the entire system and the sub 1 This work partially funded by Semiconductor Research Corporation #96 DC068 ....

I. Beer, S. Ben David, C. Eisner and A. Landver, "RuleBase: an industry oriented formal verification tool," 33th Design Automation Conference, pp. 655-660, June 1996.

....techniques[1, 2, 3] The use of this approach alone is no longer sufficient when the supporting chips become more and more complex. Formal approaches have been proposed for verifying the supporting chips. For example, they are used to prove the correctness of the cache updates and so on [4, 5]. However, the size of the circuits which can be handled by such approaches is still too limited. This paper is organized as follows: Section 2 reviews the problem of verifying the bus controller ASICs for our multiprocessor system. Section 3, presents the incremental verification approach used ....

I. Beer, et. al., Rule Base - an Industry Oriented Formal Verification Tool, Proceedings 33th ACM/IEEE Design Automation Conference, 1996.

....method are straightforward. Model checking activity in industry executes the following methodology: A verification engineer reads the specification, sets up a work environment and then proceeds to present the model checker with a sequence of properties in order to verify the design correctness [1]. The design (or implementation) on which this activity is executed can be quite large nowadays. As a result the set of properties written and verified becomes large as well, to the point that the engineer loses control over it. A large property set makes it necessary to construct tools to ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase - an industry oriented formal verification tool. In 33th Design Automation Conference, 1996. DAC.

....optimizations were implemented on top of CMU s BMC [1] 1 and the SAT checker Grasp [10, 11] without making use of features that are unique to either one of them. We benchmarked the various optimizations, and also compared them to results achieved by RuleBase, IBM s BDD based Model Checker [7, 6]. RuleBase is considered one of the strongest verification tools on the market, and includes most of the reductions and BDD optimizations that have been published in recent years. The benchmark s database included 13 randomly selected real life designs from IBM s internal benchmark set. ....

C. Eisner A. Landver I. Beer, S. Ben-David. RuleBase: An industry oriented formal verification tool. In Proc. Design Automation Conference 96 (DAC96), 1996.

....As for combinatorial circuits we need a method to find such a variable order before OBDD computations start. Here a greedy type heuristic has been proposed by Touati et al. 17] To improve variable orders dynamically, the state of the art model checking programs (SMV [12] VIS [5] Rulebase [2]) provide variants of Rudell s [16] sifting algorithm, like group sifting and symmetric sifting. The advantage of sifting is that it often produces very good orders, but for large circuits it is very time expensive. Another obstacle in model checking has been the computation of the monolithic ....

I. Beer, S. Ben-David, C. Eisner, A. Landver; Rulebase: an industry-oriented formal verification tool. Preprint 1996, IBM Haifa Research Labaratory, Israel.

....1 and the SAT checker Grasp [11, 12] without making use of features that are unique to either one of them. 1 We distinguish between the tool BMC and the method BMC. We benchmarked the various optimizations, and also compared them to results achieved by RuleBase, IBM s BDD based Model Checker [1, 2]. RuleBase is considered one of the strongest verification tools on the market, and includes most of the reductions and BDD optimizations that have been published in recent years. The benchmark s database included 13 randomly selected reallife designs from IBM s internal benchmark set. ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. RuleBase: An industry oriented formal verification tool. In Proc. Design Automation Conference 96 (DAC96), 1996.

....to conjunct the BDD with its slice after reconstructing it. 6 Experimental results In this section we report initial performance results of using our approach. We implemented our partitioned BDD and embedded it in an enhanced version of McMillan s SMV [7] due to IBM Haifa Research Laboratory [2]. Our parallel testbed includes 32 RS6000 machines, each consisting of a 266MHz PowerPC processor and 256MB memory. The communication between the nodes consists of a 16Mbit second token ring. The nodes are non dedicated; i.e. they are mostly workstations of employees who would often use them ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase: an industry-oriented formal verification tool. In 33rd Design Automation Conference, pages 655--660, 1996.

....can be performed on the sub circuit to simplify away the parts of the sub circuit that is irrelevant to the property. The property specific model extraction is done by an automatic tool that was independently developed at Intel. The tool seems to be very similar to the per function reduction in [BBDEL96] Several of the arithmetic algorithms used in the FPU are inherently iterative. For example, the square root and division computations begin by generating an initial result consisting of a few high order bits, then refining the initial result in successive iterations by computing lower order ....

R.E. I. Beer, S. Ben-David, C. Eisner, and Avner Landver. Rulebase: an industry-oriented formal verification tool. In Proceedings of the 33rd Design Automation Conference. IEEE Computer Society Press, June 1996.

....can be performed on the sub circuit to simplify away the parts of the sub circuit that is irrelevant to the property. The property specific model extraction is done by an automatic tool that was independently developed at Intel. The tool seems to be very similar to the per function reduction in [BBDEL96] Several of the arithmetic algorithms used in the FPU are inherently iterative. For example, the square root and division computations begin by generating an initial result consisting of a few high order bits, then refining the initial result in successive iterations by computing lower order ....

R.E. I. Beer, S. Ben-David, C. Eisner, and Avner Landver. Rulebase: an industryoriented formal verification tool. In Proceedings of the 33rd Design Automation Conference. IEEE Computer Society Press, June 1996.

....a mechanism for automatic error detection. In [22] a tool environment is described for the automatic execution of test scripts on VHDL components. There is no support for the automation of test script generation itself. Finally, there exist many tools for the verification of VHDL designs (e.g. [3, 4, 5]) Each of them maps VHDL code to some semantical domain, on which the verification algorithms operate. It may be worthwhile to see whether our approach can benefit from techniques used in these tools. ....

I. Beer, Sh. Ben--David, C. Eisner, and A. Landver. RuleBase: an industry-oriented formal verification tool. In: Proceedings of the 33rd ACM Design Automation Conference, Las Vegas, NV, USA, 1996.

....Institut fur Informatik, Humboldt Universitat zu Berlin, Unter den Linden 6, 10099 Berlin, Germany. 2 Mathias Block, Clemens Gropl, Harry Preu , Hans Jurgen Promel, Anand Srivastav improve variable orders dynamically, the state of the art model checking programs (SMV [19] VIS [5] Rulebase [2]) provide variants of Rudell s [26] sifting algorithm. The big advantage of sifting is that it often produces very good orders, but for large circuits it is time expensive. Another obstacle in model checking has been the computation of the monolithic transition relation. Burch, Clarke and Long ....

I. Beer, S. Ben-David, C. Eisner, A. Landver; Rulebase: an industry-oriented formal verification tool. Preprint (1996), IBM Haifa Research Labaratory, Haifa, Israel.

....of an automotive chip we will refer to as FIRE. Verdict has been extensively used to verify commercial designs [2] In the past few years, as model checking has become a popular method for verifying sequential designs, several case studies of verification of commercial designs have been published [3, 4, 5]. This work is intended to be a case study in which several aspects of formal verification of commercial hardware designs are highlighted. In this work, close interaction with the designer resulted in the identification of a very complex property to be verified ona relatively large design. A ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver, "RuleBase: An IndustryOriented Formal Verification Tool," in Proc. of the Design Automation Conf., (Las Vegas, NV), pp. 655--660, June 1996.

.... the University of Colorado at Boulder unifies the mentioned verification techniques for finite state machines and techniques for synthesis of VLSI circuits [8] Meanwhile, there are also commercial systems, e.g. CVE (Circuit Verification Environment) by Siemens [5] or the system RuleBase by IBM [2] which is built on top of SMV. 6 Variants and Extensions of OBDDs For further improving the efficiency of the data structures, several variants and extensions of OBDDs have been proposed. For some specific application fields, these refined models are better suited than the classic OBDDs. We ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. RuleBase: An industry-oriented formal verification tool. In Proc. 33rd ACM/IEEE Design Automation Conference (Las Vegas, NV), pages 655--660, 1996.

....existing techniques. As we show, this reduction alone has reduced the number of state variables by more than one half, and has enabled formal verification of the IBM Gigahertz Processor, which would not have been feasible otherwise. This abstraction is now part of the model checker RuleBase [4]. In addition, designers and verification engineers prefer to reason about the the full cycle models. The optimality of the algorithm results from the identification of minimal dependent layers (MDL) of latches, and removing all L1s or all L2s per MDL. Definition 1. A dependent layer is a set of ....

....two abstracted models to demonstrate the validity of the abstraction for CTL formulae. In Sect. 4 we introduce the algorithm used to perform the netlist reduction, and demonstrate its optimality. In Sect. 5 we give some experimental results of the use of this algorithm as implemented in RuleBase [4] for application to IBM s Gigahertz Processor. 2 Half Cycle versus Full Cycle Models Consider the netlist, denoting a MDL, shown in Fig. 2. All nets and primitives may be vectors. o n k m m n PI(0. k 1) A(0. m 1) B(0. m 1) D(0. n 1) PO(0. o 1) f1 f2 f3 C(0. n 1) L1 L2 Fig. 2. Dual Phase ....

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I. Beer, S. Ben-David, C. Eisner, and A. Landver. RuleBase: an Industry-Oriented Formal Verification Tool. In Proc. Design Automation Conf., June 1996.

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I. Beer, S. Ben-David, C. Eisner, and A. Landver. RuleBase: An industry-oriented formal verification tool. In Design Automation Conference, pages 655--660, June 1996.

....author was a member of the Formal Methods Group at IBM Haifa Research Laboratory. of formal verification projects in which RuleBase was deployed in a variety of ways according to the aforementioned methodology. Section 5 summarizes and concludes. 2 The RuleBase formal verification tool RuleBase [BBEL96] is a formal verification tool developed by the IBM Haifa Research Laboratory. It is based on SMV [McM93] the symbolic model checker developed by Ken McMillan at Carnegie Mellon University. RuleBase was described in [BBEL96] we will only briefly touch on some important points here. The ....

....and concludes. 2 The RuleBase formal verification tool RuleBase [BBEL96] is a formal verification tool developed by the IBM Haifa Research Laboratory. It is based on SMV [McM93] the symbolic model checker developed by Ken McMillan at Carnegie Mellon University. RuleBase was described in [BBEL96]; we will only briefly touch on some important points here. The verification process with RuleBase takes three inputs. The first input is the design, which can be coded in either VHDL or Verilog. The second input is the environment, which describes the legal input sequences of the design under ....

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I. Beer, S. Ben-David, C. Eisner, A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool", in Proc. 33 rd Design Automation Conference 1996, pp. 655660.

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I. Beer, S. Ben-David, C. Eisner and A. Landver, "RuleBase: An Industry-Oriented Formal Verification Tool", Proceedings of the Design Automation Conference, DAC'96.

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I. Beer, S. Ben-David, C. Eisner, A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool", in Proc. 33 rd Design Automation Conference 1996, pp. 655-660.

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I. Beer, S. Ben-David, C. Eisner, A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool", in Proc. 33 rd Design Automation Conference 1996, pp. 655-660.

....this price is negligible with respect to the benefits of on the fly model checking. Our experience also shows that well over 80 of the formulas needed for a typical hardware design can be verified with the above on the fly method. The results of this paper were implemented in 1995 in RuleBase [BBEL], which is an IBM model checker based on SMV. RuleBase reads formulas in RCTL and decides whether it is possible to verify them on the fly. Formulas that can not be verified on thefly are evaluated using the original CTL model checking algorithm. A large number of errors were detected by RuleBase ....

....power (i.e. ease of use) The following formula is an example of RCTL relative ease of use. AG(fwb a(v r v wb r)g(d) The CTL version of this formula is AG( w (EX(E[bU (a (EX( E[vU (r :d) E[vU (w (EX(E[bU (r :d) Sugar is the RuleBase specification language [BBEL]. Many useful Sugar operators are easily defined in RCTL. The formula until p (weak until) means that on all paths, is true until p is true, but p could be false forever (in which case stays true forever) In RCTL, until p is expressed by f:p :pg( The next event(p) operator states ....

I. Beer, S. Ben-David, C. Eisner, A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool", in Proc. 33 rd Design Automation Conference 1996, pp. 655-660.

....model checking to VLC code In order to apply symbolic model checking to VLC code, it is necessary to translate VLC to the input language of the symbolic model checker. Here we describe the translation to the language EDL, a dialect of SMV [McM93] accepted by the symbolic model checker RuleBase [BBEL96]. The explanations which follow use the Little Yard of [GKV94] in VLC (Figure 2) and EDL (Figure 3) 1 DIRECT INPUT SECTION 2 I 3 OUTPUT SECTION 4 Pr Pn A B C 5 CODE SYSTEM SECTION 6 CmdA CmdB CmdC Cmdr 7 CURRENT RESULT SECTION 8 E 9 SELF LATCHED PARAMETER SECTION 10 TIMER EXPRESSION ....

....show how to make use of locality to generate a true counter example for a robust system when the symbolic steps cause state space explosion. The method heuristically searches for the inputs which are not needed in the counterexample. It then sets these to 0 and uses pre model checking reductions [BBEL96] to reduce the size of the model. The method is as follows: Set half of the inputs to 0, check the formula. Probably the result finds that the formula is true. This is inconclusive, so free up some of the inputs and rerun. If the run does not terminate quickly (i.e. starts a fixed point ....

[Article contains additional citation context not shown here]

I. Beer, S. Ben-David, C. Eisner, A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool", in Proc. 33 rd Design Automation Conference 1996, pp. 655-660.

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I. Beer, S. Ben-David, C. Eisner, A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool", in Proc. 33 rd Design Automation Conference 1996, pp. 655-660.

....of the state space. This makes the distributed counterexample generation somewhat tricky: we need to track the steps backwards while switching different slices and maintaining the memory requirement at a low level. We implemented our method inside the high performance verification tool RuleBase [1], developed by the IBM Haifa Research Lab. We used a distributed, non dedicated, slow network interconnection system of 32 standard workstations. The performance results show that our method scales well. Large examples that could not fit into the memory of a single machine terminate using the ....

....other hand, we found the optimization in expression 11 to have no significant advantage over the one in expression 10. 4 Experimental Results In this section we report on the performance evaluation of our approach. We implemented our method inside the high performance verification tool RuleBase [1], 10 which is based on McMillan s SMV [15] and developed by the IBM Haifa Research lab. Our parallel test bed includes 32 RS6000 machines, each consisting of a 225 MHz PowerPC processor and 512 MB memory. The communication between the nodes consists of a 100 Mbit second token ring. We ....

I. Beer, S. Ben-David, C. Eisner, and A. Landver. Rulebase: An Industry-Oriented Formal Verification Tool. In 33rd Design Automation Conference, pages 655--660, 1996.

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I. Beer, S. Ben-David, C. Eisner, and A. Landver, "RuleBase: an Industry-Oriented Formal Verification Tool," DAC'96.

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I. Beer, S. Ben-David, C. Eisner, and A. Landver. RuleBase: An industry-oriented formal verification tool. In Design Automation Conference, pages 655--660, June 1996. 46

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