A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. Rabaey, "Evaluation of a Low-Power Reconfigurable DSP Architecture," Proceedings of the Reconfigurable Architectures Workshop, pp. 55-60, 1998. Home/Search Document Details and Download
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Reconfigurable Hardware in Wearable Computing Nodes - Plessl, Enzler, Walder.. (2002) (5 citations) (Correct)
....efficient than processors, provided that the application matches well the spatial structures of FPGAs and reveals a sufficient amount of parallelism. Mencer et al. 3] compared different implementations of the IDEA cryptography algorithm on RISC and DSP processors and on an FPGA. Abnous et al. [4] performed similar studies on finite and infinite impulse response filters (FIR, IIR) Table 1 summarizes the results and gives throughput and energy efficiency for each application. For IDEA, the throughput is measured in million encrypted bits per second, for FIR and IIR the throughput is ....
....the FPGAs achieved a better energy efficiency than the embedded RISC processor. The DSPs outperformed the FPGAs in energy efficiency for FIR and IIR, because these filters perfectly match the DSP architectures. Recently, hybrid CPUs that integrate FPGAs with CPU Type Device IDEA [3] FIR [4] IIR [4] Mbit s] Mbit Ws] Mtap s] Mtap Ws] Mtap s] Mtap Ws] RISC StrongARM SA 110 32.0 32.0 9.9 26.7 1.5 3.6 DSP TI TMS320C6x 53.1 8.9 TI TMS320C2xx 20.0 769.2 1.0 52.4 FPGA Xilinx XC4020XL 528.0 167.6 Xilinx XC4003A 30.0 454.5 2.1 9.7 Table 1. ....
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A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. Rabaey. Evaluation of a low-power reconfigurable DSP architecture. In Proc. Reconfigurable Architectures Workshop (RAW'98), volume 1388 of Lecture Notes in Computer Science, pages 55--60. Springer, 1998.
The Design of a System Architecture for Mobile Multimedia Computers - Havinga (2000) (Correct)
....is highly insufficient because all processors must communicate over the same bus. Making use of function level parallelism can increase the processing performance and efficiency. Abnous and Rabaey propose an architecture for signal processing applications that is flexible and uses low power [1]. The architecture consists of a control processor surrounded by a heterogeneous array of autonomous, special purpose satellite processors. The computational demand on the control processor is minimal, its main task is to configure the system and manage the overall control flow of a given ....
Abnous A., Seno K., Ichikawa Y., Wan M., Rabaey J.: "Evaluation of a low-power reconfigurable DSP architecture", proceedings 5 Reconfigurable Architectures workshop (RAW'98), March 30, 1998, Orlando, USA. (URL: http://xputers.informatik.unikl. de/RAW/RAW98/adv_prg_RAW98.html)
Embedded System Architectures - Ernst (1998) (2 citations) (Correct)
....a reconfigurable communication network (fig. 18) The satellites can be fixed components or reconfigurable data paths. Focusing on reconfiguration for low power consumption, the authors were able to demonstrate significant improvements compared to FPGA or programmable processor implementations [41]. The Pleiades satellites may be fixed or reconfigurable components which must be adapted to the set of applications similar to the ADSs of the Prophid architecture. On the other hand, the assignment of time slots and bus switches in Prophid can be considered as reconfiguration since it is not ....
Abnous, A., Seno, K., Ichikawa, Y., Wan, M., Rabaey, J. (1998) Evaluation of a Low-Power Reconfigurable DSP Architecture. Proc. Reconfigurable Architectures Workshop, Orlando, March 1998.
Moby Dick, on the design of a Swiss-army knife of computing - Havinga (Correct)
....Other research mainly concentrated on specific topics, and did not cover the system architecture of a mobile computer as a whole. There is much research on multimedia processors, hardware accelerators, and heterogeneous multiprocessor architectures mainly targeted for DSP algorithms (e.g. [1][8] 10] In recent years much research has been done in providing QoS over a wireless link. Access protocols for these systems typically only address network performance metrics such as throughput, bit efficiency, and packet delay. However, thus far, little attention is given to energy conserving ....
Abnous A., Seno K., Ichikawa Y., Wan M., Rabaey J.: "Evaluation of a low-power reconfigurable DSP architecture", proceedings 5 th Reconfigurable Architectures workshop (RAW'98), March 30, 1998, Orlando, USA. (URL: http://xputers.informatik.uni-kl.de/RAW/RAW98/adv_prg_RAW98.html)
Reconfigurable Processors for High-Performance, Embedded.. - Paul Graham And (Correct)
....processors were able to compute with greater e#ciency than software alone, having less software overhead due to address generation, branching, and function calls and exploiting more parallelism than is possible with the processor s normal data path. One hybrid processor RL system called Pleiades [9, 10] has specifically targeted ultra low power, embedded digital signal processing. The approach fuses an ARM core with a combination of reconfigurable logic, reconfigurable data path, and or reconfigurable data flow resources. In this case, due to power and performance constraints, the RISC core is ....
Arthur Abnous, Katsunori Seno, Yuji Ichikawa, Marlene Wan, and Jan Rabaey. Evaluation of a low-power reconfigurable DSP architecture. In Proceedings of the Reconfigurable Architectures Workshop, March 1998.
Reconfigurable Mobile Multimedia Systems - Smit, Bos, Havinga, Smit (Correct)
....We experimented with a systems architecture that accommodated the required functionality, within the energy limitation constrains of a small battery powered device. This systems architecture has some similarities with the Desk Area Network in Cambridge [5] and the Pleiades project in Berkeley [1] [2]. Octopus switching fabric Display module Processor module CPU memory Network module Wireless interface MAC and data link control buffering Camera module Audio module Fig. 1. System architecture In the architecture, we have an organization of a programmable communication ....
Abnous A., Seno K., Ichikwaw Y., Wan M., Rabaey J.: "Evaluation of a Low-Power Reconfigurable DSP architecture", Proc. 5 th Reconfigurable Architectures workshop (RAW 98), March 1998.
Unknown - The Pleiades Architecture Self-citation (Abnous Wan Rabaey) (Correct)
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A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. Rabaey, "Evaluation of a Low-Power Reconfigurable DSP Architecture," Proceedings of the Reconfigurable Architectures Workshop, pp. 55-60, 1998.
Periodic Real-Time Scheduling for FPGA Computers - Danne, Platzner (2005) (Correct)
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A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. Rabaey. Evaluation of a low-power reconfigurable DSP architecture. In Proceedings of the 5th Reconfigurable Architectures Workshop (RAW), volume 1388, pages 55--60. Springer, 1998.
A Low-Power Accelerator for the SPHINX 3 Speech Recognition.. - Mathew, Davis, Fang (2003) (1 citation) (Correct)
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A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. M. Rabaey. Evaluation of a low-power reconfigurable DSP architecture. In IPPS/SPDP Workshops, pages 55--60, 1998.
Some Design Rules to Reduce Power in Microprocessors Systems - Gonzlez De Rivera (Correct)
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A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. Rabaey, "Evaluation of a low-power reconfigurable DSP architecture", Lecture Notes in Computer Science, Vol.1388, pp.55-60. Springer, 1998.
A Gaussian Probability Accelerator for SPHINX 3 - Mathew, Davis, Fang (2003) (Correct)
No context found.
A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. M. Rabaey. Evaluation of a low-power reconfigurable DSP architecture. In IPPS/SPDP Workshops, pages 55--60, 1998.
A Gaussian Probability Accelerator for SPHINX 3 - Mathew, Davis, Fang (2003) (Correct)
No context found.
A. Abnous, K. Seno, Y. Ichikawa, M. Wan, and J. M. Rabaey. Evaluation of a low-power reconfigurable DSP architecture. In IPPS/SPDP Workshops, pages 55--60, 1998.
The Case for Reconfigurable Hardware in Wearable.. - Plessl, Enzler, Walder, .. (2003) (3 citations) (Correct)
No context found.
Abnous A, Seno K, Ichikawa Y, Wan M and Rabaey J (1998) Evaluation of a low-power reconfigurable DSP architecture. In: Proceedings of the 5th Reconfigurable Architectures Workshop (RAW), Springer Lecture Notes in Computer Science 1388:55-- 60
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