PAPADOPOULOS, G. M., BOUGHTON, G. A., GRAINER, R., AND BECKERLE, M. J. *T: Integrated building blocks for parallel computing. In Proc. Supercomputing 1993 (1993), IEEE, pp. 624-635.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... overhead of memory copying at both the sender and the receiver, and eliminating the dedicated memory for message arrival, as is found on the J Machine [8] Registermapped network interfaces have been used previously in the Mars Machine [2] J Machine, and iWarp [4] and have been described by T [26] as well as Henry and Joerg [15] However, none of these systems provide protection for user level messages. Systems, like the J Machine, that provide user access to the network interface without atomicity must temporarily disable interrupts to allow the sending process to complete the message. ....

PAPADOPOULOS, G. M., BOUGHTON, G. A., GRAINER, R., AND BECKERLE, M. J. *T: Integrated building blocks for parallel computing. In Proc. Supercomputing 1993 (1993), IEEE, pp. 624-635.

....it is also very important to reduce latency by providing mechanisms for the efficient migration of data and threads between processor nodes. The ADAM s overall organization reflects this attention to migration mechanisms. Also, a careful examination of the implementation strategy outlined in [PBB93] reveals a number of important differences (and similarities) between the ADAM and T. One significant difference is ADAM s use of a queue based interface between 29 threads, with implicit synchronization through empty full bits, similar to the scheme used in the MMachine 95] T uses a ....

....architectures. TAM [CSS 91] also referred to as Active Threads in [WGQH98] and its follow on, Active Messages [vCGS92] proposes an efficient mechanism for interprocessor communication using continuations. It significantly differentiates itself from the J Machine [NWD93] Monsoon and T [PBB93] all message driven machines, by the fact that Active Messages is a purely softwareapproach to achieving high performance. vCGS92] claims that pure message driven hardware implementations are crippled by the limited number of registers available per hardware context, whereas a software emulated ....

[Article contains additional citation context not shown here]

G. A. Papadopoulos, Greiner R. Boughton, and M.J. Beckerle. *T: Integrated building blocks for parallel computing. In Proceedings of the Conference on Supercomputing, pages 623--635, 1993.

....say to adapt to the failure of a site. Several processes of the same job can be mapped to the same site, each with its own set of message passing queues. Other machines use a Parallel Job Identifier (PJID) which is added automatically to every outgoing message and verified at the destination[7]. Such schemes define monolithic protection domains in which every process can communicate with every other process in the domain. While suitable for parallel applications, it does not offer enough flexibility in a distributed environment, where a server application may want to communicate with a ....

....used by aP. aP. 1100 sBIU s copy of MemQ ComGp. 1101 CTRL s copy of Overflow. 1110 aBIU s copy of MemQ ComGp. 1111 aBIU s copy of DMA ComGp. Table 5: Encoding for ComGp field, bit[6:9] of sPAddr. sPAddr[6] differentiates between state in CTRL (sPAddr[6] 0) and in one of the BIUs. sPAddr[7] differentiates between Pas Vas (sPAddr[7] 0) and Pcp queue. The exceptions to this encoding rules are the MemQ and Overflow ComGp s, which are special ComGp s. sPAddr[8] roughly) distinguishes between resources devoted to the aP (sPAddr[8] 1) and those used by the sP. sPAddr[9] ....

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G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, Portland, Oregon, pages 624--635, Nov. 1993.

....we have implemented all the three schemes for the same source language, compiler, and the target architecture. Our source language is Id, which is a polymorphic, strongly typed, implicitly parallel programming language [Nik91] We are compiling Id for the T multiprocessor architecture [NPA92, PBGB93] and executing it on an emulator for that machine. We have chosen a very simple mark and sweep garbage collection algorithm so that the 157 cost of object identification can be clearly identified during the mark phase. The wall clock performance of the garbage collection algorithm is not our ....

....than generating compositions of a fixed set of datatype marking functions as shown above. This would clearly reduce the overhead of using higher order marking functions. 8. 5 T Implementation T is a parallel, distributed memory machine with a high performance interconnection network [NPA92, PBGB93] The T architecture extends a basic RISC instruction set with low overhead, user mode communication and synchronization primitives. The details of the architecture may be found elsewhere [Bec92] In this section, we briefly summarize some of the 5 Readers familiar with Haskell s type classes ....

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. *T: Integrated building blocks for parallel computing. In Proceedings of Supercomputing '93, 1993.

....the network fails to support a client server model of interprocess communication. The T [18] processor uses a memory coprocessor model as well. T does not include DMA facilities or coherent caches and thus does not address the interaction of these features with messaging. A recent T paper [20] has independently proposed protection mechanisms similar to FUGU s for short messages and makes the same assumptions about separating performance from correctness in scheduling. Our focus is on developing a minimal set of mechanisms that are sufficient for user level message handling and ....

Gregory M. Papadopoulos, G. Andy Boughton, Robert Greiner, and Michael J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Supercomputing '93, pages 624--635. IEEE, November 1993.

....interface designs use special purpose message instructions (e.g. a send command) in which general purpose processor registers are the operands. Some examples include the Message Driven Processor (MDP) 22] the Caltech Mosaic [24] the Henry Joerg network interface [29] and the Start ( T) [30] network interface. An exception is iWarp from CMU [23] whose systolic communication model is based on operands rather than operators. A send command is constructed by using a message register as the destination of an arithmetic operation; a receive command is constructed by using a message ....

....into how the structure of the network interface affects the overall performance of scalable systems. In particular, the CM 5 and the J machine were compared. A related study by Papadopoulos, Boughton, Greiner and Beckerle from MIT and Motorola included a comparison of the T (Star T) interface [30]. In both studies the abstracted versions of each system were evaluated and compared. The abstracted version of the CM 5 was called CM 5 and likewise the J machine was abstracted into a system called J . The CM 5 had two significant improvements over the CM 5: the maximum packet size was ....

Greg M. Papadopoulos, G. A. Boughton, R. Greiner and M. J. Beckerle. *T: integrated building blocks for parallel computing. Proc. of Supercomputing '93, Portland OR, November 1993, pp. 624-635.

.... of memory copying at both the sender and the receiver, and eliminating the dedicated memory for message arrival, as is found on the J Machine [8] Register mapped network interfaces have been used previously in the Mars Machine [2] J Machine, and iWarp [4] and have been described by T [26] as well as Henry and Joerg [15] However, none of these systems provide protection for user level messages. Systems, like the J Machine, that provide user access to the network interface without atomicity must temporarily disable interrupts to allow the sending process to complete the message. ....

Papadopoulos, G. M., Boughton, G. A., Grainer, R., and Beckerle, M. J. *T: Integrated building blocks for parallel computing. In Proc. Supercomputing 1993 (1993), IEEE, pp. 624--635.

....strongly connected block sizes can reduce the work done by the matching unit to a minimum but blocks the rest of the PE. If this occurs the parallelism being exploited by the may be insufficient to balance the machine resource utilization. 2.1. 3 Motorola MIT StarT ( T) The T [NPA92, Bec92, PBGB93, AAC94] is a scalable computer system designed to support a broad variety of parallel programming styles including those requiring finegrained synchronization. The hardware uses a customized RISC processor with a network message interface and synchronization unit tightly integrated into the ....

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Int. Conf. on Supercomputing, pages 624--635, 1993.

....message traffic, not execution time numbers. They do not show how message traffic impacts runtime. 7.2 Remote Queues With respect to Remote Queues, there are many machines that have explicit queues in the network interface or communication coprocessor. Some of these are FLASH [HKO 94] T [PBGB93] Typhoon [RLW94] and Meiko CS 2 [Che93] RQ maps well onto all of these machines. Scheiman and Schauser [SS95] independently considered some of the basic issues of RQ in their Meiko study. T provides a fairly direct implementation of RQ. The importance of user level handlers remains up for ....

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Berkerle. *t: Integrated building blocks for parallel computing. In Supercomputing, 1993.

....that a particular message cause an interrupt, e.g. when the sender urgently needs the receiver s attention. While messages are typically received by application code, this may be preceded by NIU hardware or firmware pre processing. An example is the proposed StarT system [80] based on the 88110MP [85] processors which treats each message in the system as a continuation composed of an instruction pointer (IP) and a list of parameters. Designed to be a multi threaded processor operating in a continuation passing fashion, the 88110 MP includes an NIU that pre processes each in coming continuation ....

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, Portland, Oregon, pages 624 -- 635, Nov. 1993.

....minimal NIU Design. It interfaces with the SMP bus both as a slave and master on one side and with the network on the other side. The embedded service processor does all the work and provides flexibility. ing message a Parallel Job Identifier (PJID) which is subsequently verified at the destination[25]. In particular, it allows non monolithic and non symmetric communication domains to be set up over the same physical network. The former recognizes that not all parties in a communication network are equal: some entities are more trusted and are allowed to communicate with both trusted and ....

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, Portland, Oregon, pages 624--635, Nov. 1993.

....usually shared by users, and the unpredictable changes of CPU load and network load complicate their efficient utilization for distributed parallel computing. Current research is emerging to level off the differences between multiprocessors and workstation networks. Research prototypes such as T [21] or HPAM [18] based on the Medusa host network interface [2] provide hardware support for efficient latency hiding implementations. However, since current commodity workstations and commodity networks do not offer architectural support for communication latency hiding, we consider software based ....

.... memory architectures: Prefetching [11] coherent caches [11] and relaxed memory consistency [10] are known mainly from Stanford s DASH project [17] The third approach hides communication latencies by means of additional communication hardware (processors) in distributed memory systems such as T [21] or the Intel Paragon. Now, processor designers are introducing nonblocking caches together with dynamic instruction scheduling in next generation microprocessors such as the MIPS R10000 [20] to overcome the penalty of cache misses. Multithreading has not only been investigated at the hardware ....

G. M. Papadopoulos, R. Greiner, and M. J. Beckerle. *T: Integrated building blocks for parallel computing. In Supercomputing '93, pages 624--635, Portland, Oregon, November 1993.

....is two transmit and two receive queues. coscheduling approaches[41] The virtual destination queue name space approach is more general than other machines approach of using a Parallel Job Identifier (PJID) which is added automatically to every outgoing message and verified at the destination[36]. The latter scheme defines monolithic protection domains in which every process can communicate with every other process in the domain. While suitable for parallel applications, it does not offer enough flexibility in a distributed environment, where a server application may want to communicate ....

....with individual instructions. Examples of processors with integrated network interfaces include transputers[45] the iWarp systolic processor[6, 7] dataflow processors like Monsoon[15] and the EMC R[38] and hybrid processors such as the MDP[16] M machine[17] and the MIT Motorola 88110MP[36]. The Alewife[1] is an example of a network interface on the L1 cache interface. Alewife supports multi part message specification and its Sparcle processor provides hardware multi threading. Race conditions during access to network interface is prevented by disabling multi threading during each ....

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, Portland, Oregon, pages 624--635, Nov. 1993.

....it only to let the operating system clear the network. A polling watchdog mode could be implemented in the FUGU system. Direct Network Interfaces. Several machines have provided direct network interfaces. These include the CM 5, the J machine, iWarp, the T interface, Alewife, and Wisconsin s CNI [20, 8, 5, 26, 1, 24]. These interfaces feature low latency by allowing the processor direct access to the network queue. Direct NIs can be inefficient unless placed close to the processor. Anticipating continued system integration, we place our NI on the processor cache bus. The CNI work shows how to partly ....

....a more distant NI by exploiting standard cache coherence schemes. Direct interface designs have mostly ignored issues of multiprogramming and demand paging. The CM 5 provides restricted multiprogramming by strict gang scheduling and by context switching the network with the processors. The T NI [26] would have included GID checks and a timeout on message handling for protection as in FUGU. The M machine [12] receives messages with a trusted handler that has the ability to quickly forward the message body to a user thread. Memory Based Interfaces. Memory based interfaces in multicomputers ....

Gregory M. Papadopoulos, G. Andy Boughton, Robert Greiner, and Michael J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Supercomputing '93, pages 624--635, November 1993.

....bus; or (iv) on the I O bus. Examples of processors with integrated network interfaces include transputers[45] the iWarp systolic processor[6, 7] dataflow processors like Monsoon[16] and the EMC R[38] and hybrid processors such as the MIT MDP[17] M machine[18] and the MIT Motorola 88110MP[36]. Currently, market forces and engineering effort dictate microprocessor design, making it extremely difficult to take this approach within a commercial microprocessor. The MIT Alewife[1] is an example of a network interface on the L1 cache interface, and the design for StarT NG[12] proposed one ....

....say to adapt to the failure of a site. Several processes of the same job can be mapped to the same site, each with its own set of message passing queues. Other machines use a Parallel Job Identifier (PJID) which is added automatically to every outgoing message and verified at the destination[36]. Such schemes define monolithic protection domains in which every process can communicate with every other process in the domain. While suitable for parallel applications, it does not offer enough flexibility in a distributed environment, where a server application may want to communicate with a ....

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, Portland, Oregon, pages 624--635, Nov. 1993.

.... advantage of the characteristics of the so called System Area Network (SAN) environment [77, 64, 81, 6, 19, 17, 29, 13] Higher performance network interfaces suitable for significantly finer grain parallel problems have been demonstrated in massively parallel processors as research prototypes [70, 7, 16, 1, 61, 2, 56] and as commercial machines [45, 69, 72] However, MPP work has largely ignored issues of mixed workloads that require multiprogramming, demand paging and interactive scheduling. A scalable workstation represents one vision of the convergence of SMP, cluster and MPP goals and technologies that ....

....intolerable to the network. We proposed a solution to the VNI problem in [50] and partly evaluated it in [51] This VNI solution is implemented in FUGU and is the focus of this thesis. Other recent network interface work addresses the VNI problem with similar goals, notably CNI [58] the T family [61, 2] and the M machine [25] These projects are described as related work in Chapter 8. ffl Second is the DMA problem. Efficient bulk transfer through messages requires the support of Direct Memory Access (DMA) hardware or equivalent functionality provided by a coprocessor. Using DMA with virtual ....

[Article contains additional citation context not shown here]

Gregory M. Papadopoulos, G. Andy Boughton, Robert Greiner, and Michael J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Supercomputing '93, pages 624--635, November 1993.

....passing and shared memory, whether they are executing on one site or across multiple sites. Each 620 is connected to an NIU through its L2 cache interface. The NIU is being designed and implemented by Motorola and its partners and was heavily influenced by the MSU functional unit of the 88110MP[14]. The NIUs provide access to a Fat tree network built out of Arctic[3] routing chips. Currently under development at MIT, the Arctic router is a 4x4 router that provides 200 megabytes sec link bandwidth. 3.1 ACD The ACD has two basic functions: i) capture global bus transactions and pass it ....

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, Portland, Oregon, pages 624--635, November 1993.

....latency hiding described here focusses on utilizing protocol idle times of machines with DMA based host network interfaces [22] it is expected that future systems make less use of the CPU for protocol processing. With such system architectures, as for example developed in the T project [17] or HPAM [13] based on the Medusa host network interface [1] even more efficient latency hiding implementations will be possible. To overcome the difficulties of communication latency and load changes in computer networks, a programming model is proposed that: 1. Supports latency hiding by means ....

G. M. Papadopoulos, R. Greiner, and M. J. Beckerle. *T: Integrated building blocks for parallel computing. In Supercomputing'93, pages 624--635, November 1993.

....A tightly coupled processor network interface is one that is integrated onto the same silicon chip as the processor; the instruction set architecture of the processor includes specific instructions for sending and receiving messages. Examples include iWarp [9] MDP (J machine) 10] and T [11]. The advantage of tightly coupled systems is an order of magnitude lower message latency than a comparable bus based interface. However, there are several disadvantages to this strategy. By placing the interface onto the processor chip, some other functionality must be eliminated or moved ....

....solution using sea of gates technology. The current design of Cranium uses the standard gang scheduling model for safe user level access [5, 13] Recently, there has been interest in studying general processor scheduling on multicomputers that have user level support for message passing [11, 14]. The idea is to let multiple user processes execute at the same time inside the same machine partition. The interaction between adaptive packet routing and general processor scheduling is interesting, and we intend to address this issue in our continuing work with Cranium. 7 Summary We present a ....

Greg M. Papadopoulos et al. *T: Integrated Building Blocks for Parallel Computing. Proc. of Supercomputing '93, Portland OR, November 1993, pp. 624-635.

....on stock processors, remains a big challenge, partly because of the fine granularity of the parallelism exploited. The Monsoon[27] project was designed to address and investigate support for fine grain parallelism, and has yielded very encouraging results[13] Our experience with Monsoon and T[24, 28], a followup project after Monsoon, suggests that provision for global shared memory is an area where both the Monsoon and T architectures can be improved. Starting with the split phase approach used in Monsoon and T, we propose to augment global memory access by including coherent global ....

.... on these experiences, and the basic requirements of any parallel computation, we suggest a desirable set of features to be incorporated in our current machine called T NG (StarT, the Next Generation) Essentially T NG has better provision for global shared memory than either Monsoon or 88110MP [28], a Motorola 88110 based implementation of the abstract T model presented in [24] Our proposal adds caching of global memory in a way that allows it to coexist with the split phase transactions and the multithreaded approach used in Monsoon and the 88110MP. The rapid improvements in stock ....

[Article contains additional citation context not shown here]

G. M. Papadopoulos, G. A. Boughton, R. Greiner, and M. J. Beckerle. ?T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, Portland, OR, Nov 1993.

....high bandwidth transfer of large messages, although its bandwidth is very competitive. Achieving low overhead sending of small messages is a more difficult objective to achieve but allows finer granularity parallel execution. Machines that have influenced us in this area are the original T project[19], MIT s Monsoon[18] ETL s EM 4[22] the J Machine[8] and the M Machine[11] StarT ng s software approach to cache coherency is shared by other projects as well. The Wisconsin Wind Tunnel[20] WWT) uses minimal hardware support 2 to implement shared memory. Network Virtual Memory[15, 14] NVM) ....

G. M. Papadopoulos et al. *T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, Portland, Oregon, pages 624--635, November 1993.

.... overhead of memory copying at both the sender and the receiver, and eliminating the dedicated memory for message arrival, as is found on the J Machine [8] Registermapped network interfaces have been used previously in the Mars Machine [2] J Machine, and iWarp [4] and have been described by T [26] as well as Henry and Joerg [15] However, none of these systems provide protection for user level messages. Systems, like the J Machine, that provide user access to the network interface without atomicity must temporarily disable interrupts to allow the sending process to complete the message. ....

PAPADOPOULOS, G. M., BOUGHTON, G. A., GRAINER, R., ANDBECKERLE, M. J. *T: Integrated building blocks for parallel computing. In Proc. Supercomputing 1993 (1993), IEEE, pp. 624--635.

.... avoiding the overhead of memory copying at both the sender and the receiver, and eliminating the dedicated memory for message arrival, as is found on the J Machine [6] Register mapped network interfaces have been used previously in the JMachine and iWarp [2] and have been described by T [20] as well as Henry and Joerg [11] However, none of these systems provide protection for user level messages. Systems, like the J Machine, that provide user access to the network interface without atomicity must temporarily disable interrupts to allow the sending process to complete the message. ....

G. M. Papadopoulos, G. A. Boughton, R. Grainer, and M. J. Beckerle. *T: Integrated building blocks for parallel computing. In Proc. Supercomputing 1993, pages 624--635. IEEE, 1993.

....the Stanford DASH [58] uses MIPS R3000s, the Cray T3D uses DEC Alphas, and the Intel Paragon uses Intel i860s. Some experimental systems use modified commercial parts. For example, the MIT Alewife uses modified Sparc microprocessors, while the MIT T planned to use modified Motorola 88110s [37]. We conclude that commodity microprocessors are the processors of choice in multis where the price performance ratio is important. High end commodity microprocessors are probably the best choice because a small sacrifice in the price performance of the node processor will be compensated for by a ....

G.M. Papadopoulos et al. *T: Integrated building blocks for parallel computing. In Proceedings of Supercomputing '93, pages 624--635, 1993.

....which provides error detection, limited error handling, and in circuit testability. 1 Introduction Arctic is a four input four output packet router implemented on a Motorola H4CP gate array chip. Arctic has all the features necessary for use in a commercial multiboard multiprocessor such as T [7, 8, 1]. It has high bandwidth (200 MBytes sec port) two priority levels, packet sizes up to 96 bytes, and extensive error detection; it has limited error handling, keeps statistics, can directly drive long PC traces, and provides significant testing support. While Arctic has special features to support ....

G.M. Papadopoulos, G.A. Boughton, R. Greiner, and M.J. Beckerle. *T: Integrated Building Blocks for Parallel Computing. In Proceedings of Supercomputing '93, November 1993.

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