Y.-T. S. Li, Sharad Malik, and Andrew Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. In IEEE Real-Time Systems Symposium, pages 254--263, 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....designer to budget enough processing power to handle worst case computational requirements and safely meet deadlines under any circumstance. Sophisticated timing analyzers can calculate safe, tight WCET bounds for tasks executing on single issue inorder pipelines with instruction and data caches [2,11,12,14,15,16,17,18,26,34,42]. However, the level of sophistication needed to safely and accurately analyze more complex architectures is formidable. Currently, there is no way to precisely specify microarchitectures with a full complement of high performance techniques (complex dynamic branch predictors, caches, deep ....

....WCET of realtime programs. Static analysis has been extended from unoptimized programs on simple CISC processors [10,29,30,33] to optimized programs on pipelined RISC processors [12,18,42] and from uncached architectures to architectures with instruction caches [2,14,16,26] and data caches [11,15,17,34]. Lundqvist and Stenstrom modified an architectural simulator to determine WCET bounds by considering alternate execution paths in parallel (instead of following a trace) combined with pruning techniques to reduce the search space [20] We fully leverage all of the above work with respect to ....

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. Real-Time Systems Symposium, pp. 254--263, Dec. 1996.

....enough to span a guideline for tradeoff decisions for partitioning, as well as to provide initial information for software development within a real time operating system. Static timing analysis is a subject of research for some time. Here, the most general approach was presented by LI et al. [4]. But in the end, all previous surveys were either limited to more basic RISC processors [4] 6] or to single architectural properties [3] 2] Moreover, most obtained results were validated by simulation and not by using a realworld environment. LIM et al. 5] first introduced a analysis ....

....initial information for software development within a real time operating system. Static timing analysis is a subject of research for some time. Here, the most general approach was presented by LI et al. 4] But in the end, all previous surveys were either limited to more basic RISC processors [4][6] or to single architectural properties [3] 2] Moreover, most obtained results were validated by simulation and not by using a realworld environment. LIM et al. 5] first introduced a analysis technique for multiple issue processors for their analysis framework ETS. But, they restricted ....

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Y.-T. S. Li, S. Malik, and A. Wolfe. Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches. In Proceedings of the 17th IEEE Real-Time Systems Symposium, pages 254--263. IEEE, December 1996.

....real time systems relies on #######knowledge of the worst case execution time (WCET) of hard real time tasks to check if the deadline of a task can be met. A safe upper bound on the WCET of a task can be provided through static analysis, dynamic analysis or even a combination of both techniques [34, 30, 15, 41, 24, 16, 1, 22, 23, 9, 29, 38]. Regardless of the methods utilized to obtain the WCET of tasks, experiments show a wide variation between longest and shortest execution times for manyembedded applications. In [38] execution times of real world embedded tasks vary by as much as 87 relative to their measured WCET. Speci ....

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. In #### ######### ####### #########, pages 254-263, December 1996.

.... it can be proved that the access always results in a cache hit, miss otherwise) Techniques to predict the worst case task behavior regarding the instruction cache can use data flow analysis on each task control flow graph [12] abstract interpretation [1] integer linear programming techniques [10], or symbolic execution [11] At the inter task level, work has been undertaken to obtain safe and precise estimates of the cache related preemption delay [9] In [9] at every possible preemption point, the blocks that will be used by each task after that point are determined by static analysis, ....

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction cache. In Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS96), pages 254--263. IEEE, IEEE Computer Society Press, Dec. 1996.

....miss causes the tasks WCETs to be largely overestimated, which may cause the schedulability analysis to fail while the system may actually be feasible. The classification methods can be based on data flow analysis [Mue00] abstract interpretation [AFMW96] integer linear programming techniques [LMW96] or symbolic execution [LS99] At the inter task level, work has been undertaken to obtain safe and precise estimates of the cache related preemption delays [LHS 98] In this work, at every possible preemption point, the blocks that will be used by each task after that point are determined ....

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction cache. In Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS96), pages 254--263. IEEE, IEEE Computer Society Press, December 1996.

....the tight bound on worst case performance of the systems. Especially, worst case performance analysis is extremely important for ecient implementation of hard real time systems in which real time constraints have to be satis ed. There are a number of previous researchefforts, for example [1, 3, 9, 10], to estimate the tight bound on worst case execution time of a given task in a single task environment. However, they cannot directly be applied for preemptivemultitask systems because they do not takeinto account intertask cache interference, called Cache Related Preemption Delay (CRPD) CRPD is ....

Y.-T. S. Li, S. Malik, and A. Wolfe, \Cache modeling for real-time software: Beyond direct mapped instruction caches," In ##### ## ######### ####### #####, pp. 254-263, 1996.

....analysis that results in underutilization of system resources. To obtain accurate prediction for modem highperformance processors, the timing effect of advanced architectural features should be taken into account. For example, several groups including Zhang et al. 15] Lim et al. 11] Li et al. [10], and Healy et al. 4] had investigated the prediction techniques for pipelined processors. However, most of existing techniques assume that processors can issue at most one instruction at each cycle, thus cannot produce accurate analysis results for modem multiple issue machines such as ....

....prediction is one of our main future research topics. All memory accesses are cache hits. This assumption is to ignore the effect of cache misses on the execution time. Since our approach does not make any assumption on the cache system, previously proposed techniques on the cache analysis [1, 11, 10] can easily be integrated with our approach. Processor can issue up to k instructions simultaneously, where k is provided as a parameter to our analysis. k is equal to or smaller than the number of functional units in the processor (i.e. k 9 in our processor model) We further assume that ....

Y. S. Li, S. Malik, and A. Wolfe. Cache Modeling for RealTime Software: Beyond Direct Mapped Instruction Caches. In Proceedings of the 17th Real-Time Systems Symposium, pages 25z1263, 1996.

....F. Mueller s static cache simulation [13] which statically simulates all possible contents of the cache by considering possible execution paths all at once. Several works use static simulation techniques to take into account architectural features such as pipelines [5, 8, 20] instruction caches [13, 11, 8, 20], cache hierarchies [13] data caches [9] and branch prediction [2] Most timing analysis approaches that integrate several of the above static simulation techniques (usually cache and pipeline) into a single static WCET analysis method lead to static WCET analysis tools that are difficult to ....

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction cache. In Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS96), pages 254263. IEEE, 1EEE Computer Society Press, Dec. 1996.

....We construct the approximative CFG with the real time systems analysis in mind, i.e. it must be safe and must be as precise as possible. The next steps, refining the CFG by constant propagation, loop reconstruction, and then performing analyses has been discussed in literature (e.g. in [6, 10, 13, 14, 15, 19, 20, 22]) A bottom up algorithm will be presented that overcomes some deficiencies of top down algorithms. Topdown algorithms rely on information about routine boundaries from executables. These are usually given as start and end addresses. It is a common compiler technique, however, to store certain ....

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches. In Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS), 1996.

....features. This is plausible because processor performance gets better. On the other hand, however, processor timing behavior becomes very complex and hard to predict. In recent years, great efforts have been made to model features like pipelines [5] instruction and data caches [5, 11], and branch prediction techniques [1] The results achieved are really amazing but they come with the cost of very complex, and therefore error prone timing analysis, and significant overestimation of the actual execution time due to the difficulties to model the performance optimizing features ....

Li, Y. S., Malik, S., and Wolfe, A. "Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches". In Q...'p#'s#ur &#uSrhy#Uvr T'+#r+T'f'+v, Dec. 1996.

.... predicted traced [ fac 61 53 25756 25600 100.61 prime 274 238 62507 61940 100.92 sort 110 104 2503726 2503646 100.00 matmul 123 103 1908 1879 101.54 circle 53 49 1945 1912 101.73 jfdctint 49 46 4587 4259 107.70 stats 148 135 150592 150578 100.01 ndes 625 540 54148 51478 105.19 In [11 13] Yau Tsun Steven Li, Sharad Malik, and Andrew Wolfe describe how integer linear programming can be used to solve the problem of finding worst case program paths and how this can be extended to cache memories and pipelines (See http: www.ee.princeton.edu yauli cinderella 3.0 ) Their work ....

....user to provide constraints separately for different contexts. In the approach of Li, Malik and Wolfe, the cache behaviour prediction with integer constraints leads to quite large sets of constraints when the level of associativity is increased, and leads to prohibitively high analysis times (see [13]) Our approach is virtually independent of the level of associativity. Everything between 1 and 8 has been tested without significant changes of analysis times. By using the results of the cache analysis based on AI (which performs very well for independent of the associativity level) the ....

[Article contains additional citation context not shown here]

Li, Y.-T. S., S. Malik, and A. Wolfe: 1996, `Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches'. In: Proceedings of the 17th IEEE Real-Time Systems Symposium.

....its response time. This effect, called cache refill penalty or cache related preemption delay must be considered in the schedulability analysis, because increases the task execution time over the precalculated WCET. Several solutions have been proposed to use cache memories in real time systems. [1,2,3,4] analyse the cache behaviour to estimate the task execution time considering the intra task interference. 5,6,7] analyse the cache behaviour to estimate the task response time considering the inter task interference, using a precalculated cached WCET. 8,9,10,11] use hardware and software ....

Li, Y. S., S. Malik, and A. Wolfe. Cache Modeling for RealTime Software: Beyond Direct Mapped Instruction Caches.Proc. of the 17th IEEE Real-Time Systems Symposium, December 1996.

....the analysis is based on information collected before or at compile time. In order to get fairly accurate estimation results, both program flow and system resource utilization must be analyzed. Since the number of feasible program execution paths can be exponential, explicit [8] and implicit [10] path enumeration techniques are proposed to identify the worst case program execution sequence efficiently. Micro architecture affects program execution time by changing instruction timing and program flow. Commonly used mechanisms in modern processors for the purpose of boosting system ....

....branch prediction is studied in [11] However, it s based on branch target buffer modeling by considering all possible program execution paths. 3. INTEGER LINEAR PROGRAMMING (ILP) BASED TIMING ANALYSIS SCHEME In this section we briefly review the ILP based bounding technique used in Cinderella [10], which is adapted as the core analysis scheme in our work. Cinderella is a timing analysis tool for simple embedded processors. It consists of two components for solving the WCET problem: program flow analysis and microarchitecture modeling. Program flow analysis characterizes the program flow ....

[Article contains additional citation context not shown here]

Y. S. Li, S. Malik and A. Wolfe, "Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches". In Proceedings of the IEEE Real-Time Systems Symposium, December 1996.

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Y.-T. S. Li, Sharad Malik, and Andrew Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. In IEEE Real-Time Systems Symposium, pages 254--263, 1996.

No context found.

Li, Y. S., S. Malik, and A. Wolfe (1996). Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches. Proc. of the 17th IEEE Real-Time Systems Symposium.

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Y.-T. Li, S. Malik, and A. Wolfe. Cache modeling for realtime software: Beyond directed mapped instructions caches. In Proc. 17th IEEE Real-Time Systems Symp., pages 254-- 263, Washington, D.C., Dec. 1996. IEEE.

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Y. S. Li, S. Malik, and A. Wolfe. Cache Modeling for RealTime Software: Beyond Direct Mapped Instruction Caches. pages 254--263, 1996.

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Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. In IEEE Real-Time Systems Symposium, pages 254--263, Dec. 1996.

No context found.

Yau-Tsun Steven Li, Sharad Malik, and Andrew Wolfe. Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches. In Proceedings of the IEEE Real-Time Systems Symposium, December 1996.

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Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. IEEE Real-Time Systems Symposium, pages 254--263, Dec. 1996.

No context found.

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for realtime software: Beyond direct mapped instruction caches. In IEEE Real-Time Systems Symposium, pages 254--263, Dec. 1996.

No context found.

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches. In Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS), 1996.

No context found.

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches. In Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS), 1996.

No context found.

Y.-T. S. Li, S. Malik, and A. Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. In IEEE Real-Time Systems Symposium, pages 254-263, December 1996.

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Y. S. Li, S. Malik, and A. Wolfe. Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches. Proc. of the 17 IEEE Real-Time Systems Symposium, 1996.

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