Kastrup, Bernardo et al, ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator, Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, Napa Valley,USA, April 1997 http://pww.natlab.research.philips.com:25151/confcomp/index.htm  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of the best code sections to map on hardware. Typically, identification work has been published with a specific architecture in mind and in most cases it has been directed to a special case of AFUs: those which are implemented in a lattice configurable after manufacturing, such as FPGAs [15, 9, 1, 12, 19, 11, 2]. 1.1 Goals of the Present Work When designing compilers to generate AFUs a fundamental choice needs to be made between mapping exclusively sections of the dataflow computation (clusters of elementary arithmetic or logic operations) or mapping more complex hardware add ons that include the ....

....the same ASIC technology as the main processor complex. In this respect, the present work strives to make the technology assumptions as transparent as possible. Other data concerning specialised functional units have been published in connection with reconfigurable computing (see, for instance, [15, 9, 1, 12, 11, 2]) Again, we see the need for more general data not influenced by the specific techniques developed by the authors to identify the clusters of operations to be mapped on hardware, nor dependent on some strong microarchitectural limitations dictated by the specific hardware considered. Some of the ....

B. Kastrup, A. Bink, and J. Hoogerbrugge. ConCISe: A compiler-driven CPLD-based instruction set accelerator. In Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, Calif., Apr. 1999.

....for constraints on the number of inputs and outputs of the clusters. The work in [2] is very similar from the identification perspective, although the overall goal and architectural context is rather di#erent. Work in reconfigurable computing is often more in line with our goal (e.g. 14] 1] [12], 18] Yet, identification algorithms are relatively simple and almost invariably target clusters producing a single result. Usually, clusters or subgraphs are somehow grown from their output nodes by adding predecessors until some constraints are violated. More formal approaches such as the one ....

B. Kastrup, A. Bink, and J. Hoogerbrugge. ConCISe: A compiler-driven CPLD-based instruction set accelerator. In Proc. of the 5th IEEE Symp. on Field-Programmable Custom Computing Machines, Napa Valley, Calif., Apr. 1999.

....the general purpose processor flexibility to achieve medium performance for a large class of applications, and FPGA capability to implement applicationspecific computations. There have been various attempts to attach a reconfigurable core to a processor, most of them involving a simple processor [1, 2, 3]. This paper presents an experiment which aims to evaluate the potential impact on performance yielded by augmenting a TriMedia CPU64 processor with a multiple context FPGA core. We first propose an extension of the TriMedia CPU64 architecture, which encompasses a multiple context FPGAbased ....

Kastrup, B., A. Bink, and J. Hoogerbrugge, "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator," in IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, 1999, pp. 92--100.

....cosine transform, VLIW processors, field programmable gate array. I. INTRODUCTION A common issue addressed by computer architects is the range of performance improvements that may be achieved by augmenting a general purpose processor with a reconfigurable core [1] 2] 3] 4] 5] 6] [7]. The basic idea of such approach is to exploit both the general purpose processor capability to achieve medium performance for a large class of applications, and FPGA flexibility to implement application specific computations. This paper presents the implementation of an 8 point Inverse Discrete ....

Bernardo Kastrup, A. Bink, and J. Hoogerbrugge, "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator," in (FCCM '99), Napa Valley, California, April 1999, pp. 92--100.

.... with communication between the microprocessor and the reconfigurable logic block to become the bottleneck within the system [6] This overhead can be reduced by caching multiple configurations within the reconfigurable function blocks at the cost of more expensive and less flexible hardware [15] [18], 31] Hybrid architectures targeted at accelerating symmetric key cryptography include ConCISe, Garp, and MorphoSys [16] 18] 26] Generalized reconfigurable architectures consist of an interconnected network of configurable logic and storage elements where the granularity of the ....

.... This overhead can be reduced by caching multiple configurations within the reconfigurable function blocks at the cost of more expensive and less flexible hardware [15] 18] 31] Hybrid architectures targeted at accelerating symmetric key cryptography include ConCISe, Garp, and MorphoSys [16] [18], 26] Generalized reconfigurable architectures consist of an interconnected network of configurable logic and storage elements where the granularity of the architecture is dependent upon the target application. Architectures are typically distinguished based on the control of processing ....

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B. Kastrup, A. Bink, and J. Hoggerbrugge. ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. In Seventh Annual IEEE Symposium on FieldProgrammable Custom Computing Machines, FCCM '99, pages 92--101, Napa Valley, California, USA, April 21-23 1999. IEEE, Inc.

.... with communication between the microprocessor and the reconfig urable logic block often becomes the bottleneck within the system [27] This overhead can be reduced by caching multiple configurations within the reconfigurable function blocks at the cost of more expensive and less flexible hardware [68, 81, 151, 152]. Hybrid ar chitectures have been targeted at accelerating applications such as symmetric key cryp tography, digital signal processing, data compression, image processing, video processing, multimedia, block matching, automated target recognition, and wireless communications [9, 20, 21, 30, 35, ....

.... [68, 81, 151, 152] Hybrid ar chitectures have been targeted at accelerating applications such as symmetric key cryp tography, digital signal processing, data compression, image processing, video processing, multimedia, block matching, automated target recognition, and wireless communications [9, 20, 21, 30, 35, 68, 69, 73, 81, 116, 120, 123, 134, 153]. Examples of hybrid architectures include A7, Chimaera, ConCISe, DREAM, ES, Garp, MorphoSys, NAPA, OneChip, PRISC, and ReRISC. A7 and E5 The Triscend A7 32 bit configurable system on chip consists of an ARM7TDMI processor core combined with a Configurable System Logic (CSL) programmable matrix. ....

[Article contains additional citation context not shown here]

B. Kastrup, A. Bink, and J. Hoggerbrugge. ConCISe: A Compiler-Driven CPLD- Based Instruction Set Accelerator. In Seventh Annual IEEE Symposium on Field- California, USA, April 21-23 1999. IEEE, Inc.

....approach is to exploit both the general purpose processor capability to achieve medium performance for a large class of applications, and FPGA flexibility to implement application specific computations. Thus far FPGA augmented processors have predominantly assumed a simple general purpose core [1 4]. Considering the class of VLIW machines, two general research questions may be raised: What are the influences of reconfigurable arrays on the performance of commercially available VLIW processors What are the architectural changes needed for incorporating the reconfigurable array into ....

Kastrup, B., Bink, A., Hoogerbrugge, J.: ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. In: IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, (1999) 92--100.

....to achieve medium performance for a large class of applications, and FPGA flexibility to implement application specific computations. There have been various attempts to attach a reconfigurable core to a host processor in the last decade, most of them involving a simple general purpose processor [1, 2, 3, 4, 5, 6, 7, 8, 9]. This paper presents an experiment which aims to assess the potential impact on performance yielded by augmenting a TriMedia CPU64 processor with a reconfigurable core. We first propose the skeleton of an extension of TriMedia CPU64 architecture, which encompasses a Reconfigurable Functional ....

B. Kastrup, A. Bink, and J. Hoogerbrugge, "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator, " Proceedings of 7th Annual IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM '99), Napa Valley, California, Apr. 1999, pp. 92--100.

....integrating the reconfigurable hardware so closely that it is just another functional unit within the pipeline of the processor. Such projects include the PRISC design of Razdan at Harvard University [63] Chimaera at Northwestern University [29, 83] and ConCISe at Philips Research Laboratories [41]. In these designs, the reconfigurable hardware has no separate data state of its own; instead, like other functional units in a processor, data inputs are obtained from the register file and results stored back there. Without any internal registers, the reconfigurable functional units support ....

....the freedom to integrate reconfigurable hardware with the processor, some designers have gone all the way and added a reconfigurable array as another functional unit in the processor pipeline. As noted in Section 2.5. 2, examples in the literature include PRISC [63] Chimaera [29, 83] and ConCISe [41]. With such a design, array inputs are naturally taken from processor registers and results written back to the register file, just as for other pipeline functional units (Figure 3.1(a) By adding one or more processor instructions of the form rd = reconfigop(ra,rb) the reconfigurable array can ....

[Article contains additional citation context not shown here]

Bernardo Kastrup, Arjan Bink, and Jan Hoogerbrugge. ConCISe: A compiler-driven CPLD-based instruction set accelerator. In Kenneth L. Pocek and Je#rey M. Arnold, editors, Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pages 92--101, April 1999.

.... components and the calculation of the incremental configurations that must be loaded [Luk97a, Shirazi98] Alternately, similar operations can be grouped together to form a single configuration which contains extra control circuitry in order to implement the various functions within the group [Kastrup99]. By creating larger configurations out of groups of smaller configurations, the configuration overhead of partial reconfiguration is reduced because more operations can be present on chip simultaneously. However, there are some area and execution penalties imposed by this method, creating a ....

B. Kastrup, A. Bink, J. Hoogerbrugge, "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator", IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.

.... host REMARC [19] Garp [20] OneChip 98 [10] URISC [21] Nano Processor (load time reconfiguration) 22] Gilson s CCM [23] CCSimP (load time reconfiguration) 24] Xputer rALU (load time reconfiguration) 25] b) Without explicit 6 instruction: PRISC [26] OneChip [9] ConCISe [27], OneChip 98 [10] DISC [28] Multiple RISA [29] Chimaera [30] c) Not obvious information about an explicit 6 instruction: Virtual Computer [31] Functional Memory [32] NAPA [33] 2. Horizontal microcoded CCMs (a) With explicit instruction: CoMPARE [34] Alippi s VLIW [35] ....

B. Kastrup et al., "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator," in Proc. IEEE Symp. on FPGAs for Custom Computing Machines, Napa Valley, California, 1999, pp. 92--100.

.... components and the calculation of the incremental configurations that must be loaded [Luk97a, Shirazi98] Alternately, similar operations can be grouped together to form a single configuration which contains extra control circuitry in order to implement the various functions within the group [Kastrup99]. By creating larger configurations out of groups of smaller configurations, the configuration overhead of partial reconfiguration is reduced because more operations can be present on chip simultaneously. However, there are some area and execution penalties imposed by this method, creating a ....

B. Kastrup, A. Bink, J. Hoogerbrugge, "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator", IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.

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Kastrup, Bernardo et al, ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator, Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, Napa Valley,USA, April 1997 http://pww.natlab.research.philips.com:25151/confcomp/index.htm

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B. Kastrup, A. Bink, and J. Hoogerbrugge. ConCISe: A compiler-driven CPLD-based instruction set accelerator. In Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, Calif., Apr. 1999. 16

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B. Kastrup et al., \ConCISe: A Compiler-Driven CPLDBased Instruction Set Accelerator," in Proc. IEEE Symp. on FPGAs for Custom Computing Machines, Napa Valley, California, 1999, pp. 92-100.

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Bernardo Kastrup, A. Bink, and J. Hoogerbrugge, "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator," in (FCCM '99), Napa Valley, California, April 1999, pp. 92--100.

No context found.

B. Kastrup, A. Bink, and J. Hoogerbrugge. ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. In K. L. Pocek and J. M. Arnold, editors, IEEE Symposium on FPGAs for Custom Computing Machines, pages 92--100, Napa Valley, California, April 1999.

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B. Kastrup, A. Bink, and J. Hoogerbrugge. ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. In Proc. 7th IEEE Symp. on FCCMs, pp. 92-100, Napa Valley, California, 1999.

No context found.

B. Kastrup, A. Bink, and J. Hoogerbrugge. ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. In Proc. 7th IEEE Symp. on FCCMs, pp. 92-100, Napa Valley, California, 1999.

No context found.

Kastrup, B., Bink, A., Hoogerbrugge, J.: ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator. In: IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, California, (1999) 92--100.

No context found.

B. Kastrup, A. Bink, and J. Hoogerbrugge, "ConCISe: A Compiler-Driven CPLD-Based Instruction Set Accelerator, " Proceedings of 7th Annual IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM '99), Napa Valley, California, Apr. 1999, pp. 92--100.

No context found.

Bernardo Kastrup, Arjan Bink, and Jan Hoogerbrugge. ConCISe: A compiler-driven CPLD-based instruction set accelerator. In Proceedings of the 5th IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, Calif., April 1999.

No context found.

B. Kastrup, A. Bink, and J. Hoogerbrugge. ConCISe: A compiler-driven CPLD-based instruction set accelerator. In Proceedings of the 5th IEEE Symposium on FieldProgrammable Custom Computing Machines, Napa Valley, Calif., Apr. 1999.

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