Hutchings, B., Bellows, P., Hawkins, J., Hemmert, S., "A CAD Suite for High-Performance FPGA Design", Proc. IEEE Symp. on FCCM, Napa Valley (CA), 1999  Home/Search   Document Details and Download   Summary   Related Articles   Check

....applet for IP evaluation and delivery will be provided. Next, various scenarios for IP delivery applets will be suggested and the paper will conclude with directions for future work. 2. JHDL JHDL is a open source design environment developed at BYU used for creating high performance FPGA designs[3, 4]. Based on the Java programming language, users create FPGA designs by writing Java programs that instance FPGA components and wires found within the supported JHDL libraries. These Java files are compiled using conventional Java compilation tools and simulated within the Java Virtual Machine ....

B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting. A CAD suite for high-performance FPGA design. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 12--24. IEEE Computer Society, IEEE, April 1999.

....not all designers can be intimately familiar with every reconfigurable architecture, some design tools abstract the specifics of the target architecture. Creating a circuit using a structural design language involves describing a circuit using building blocks such as gates, flip flops and latches [Bellows98, Gehring98, Hutchings99]. The compiler then maps these modules to one or more basic components of the architecture of the reconfigurable system. Structural VHDL is one example of this type of programming, and commercial tools are available for compiling from this language into vendor specific FPGAs [Synplicity99] ....

....drawing or with a traditional waveform output. By examining these values, the operation of the circuit can be verified for correctness, and conflicts on individual wires can be seen. A number of simulation and debugging software systems have been developed which use some or all of these techniques [Arnold92, Bellows98, Gehring96, Hutchings99, Lysaght96, McKay99, Vasilko99]. 4.10 Software Summary Reconfigurable hardware systems require software compilation tools to allow programmers to harness the benefits of reconfigurable computing. On one end of the spectrum, circuits for reconfigurable systems can be designed manually, leveraging all application specific and ....

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B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, M. Rytting, "A CAD Suite for High-Performance FPGA Design", IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.

....the program How to verify the compiler and module generator libraries HandelC[5] is a hardware (FPGA) programming language based on communicating sequential processes[4] Every expression implies a latency of one clock cycle. Areatime tradeoffs can be explored by rewriting expressions. JHDL[11] and Pebble[8] are examples for structural languages for FPGAs on the PAM Blox level. JBITS[12] is an object oriented environment on the FPGA configuration bitstream level.Neither JHDL nor Pebble offer operator overloading. Instead, expressions are constructed by nesting function calls. Novel ....

.... = in[2] coef[1] in[6] coef[6] 256) 9; t[4] in[1] coef[0] in[7] coef[5] 256) 9; t[5] in[1] coef[5] in[7] coef[0] 256) 9; t[6] in[3] coef[2] in[5] coef[7] 256) 9; t[7] in[3] coef[7] in[5] coef[2] 256) 9; t[8] t[0] t[3] 2) 2; t[9] t[1] t[2] 2) 2; t[10] t[1] t[2] 2) 2; t[11]= t[0] t[3] 2) 2; t[0] t[4] t[6] 2) 2; t[1] t[5] t[7] 1) 1; t[2] t[4] t[6] 1) 1; t[3] t[5] t[7] 2) 2; t[4] t[1] t[2] 1) 1) coef[3] 8192) 14; t[5] t[1] t[2] 1) 1) coef[3] 8192) 14; out[0] t[8] t[0] 4) 3; out[1] t[9] t[4] 4) 3; out[5] t[10] t[5] 4) 3; ....

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P. Bellows, B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, M. Rytting, A CAD Suite for HighPerformance FPGA Design, IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, 1999.

....times of months to years. Reconfigurable computing, on the other hand, requires a hardware design process with a user interface similar to high level programming languages. As a response to this gap researchers developed general purpose programming languages for FPGAs such as HandelC[4] JHDL[8], and Pebble[6] To achieve high performance circuits, a program for FPGAs needs to express a functional view just like microprocessor programs, but also a physical view corresponding to the architecture of the FPGA circuit. Therefore, general purpose compilation tools for FPGAs try to include the ....

.... HWint BITS t[9] temp; void IDEA: build( t[1] ideaKCM16(in[0] key[0] t[2] in[1] key[1] t[3] in[2] key[2] t[4] ideaKCM16(in[3] key[3] tmp = t[1] t[3] tmp = ideaKCM16(tmp , key[4] t[7] tmp (t[2] t[4] t[8] = ideaKCM16(t[7] key[5] tmp = t[8] tmp) out[0] t[1] t[8] out[3] t[4] tmp; tmp = tmp t[2] out[1] t[3] t[8] out[2] tmp; The resulting (see Table II) stream architecture with 14 arithmetic units and 8 automatically generated and scheduled FIFO buffers is shown in Figure II. ....

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P. Bellows, B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, M. Rytting, A CAD Suite for High-Performance FPGA Design, Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.12-24, Apr. '99, IEEE CS '99.

....times of months to years. Reconfigurable computing, on the other hand, requires a hardware design process with a user interface similar to high level programming languages. As a response to this gap researchers developed general purpose programming languages for FPGAs such as HandelC[4] JHDL[8], and Pebble[6] To achieve high performance circuits, a program for FPGAs needs to express a functional view just like microprocessor programs, but also a physical view corresponding to the architecture of the FPGA circuit. Therefore, general purpose compilation tools for FPGAs try to include the ....

.... HWint BITS t[9] temp; void IDEA: build( t[1] ideaKCM16(in[0] key[0] t[2] in[1] key[1] t[3] in[2] key[2] t[4] ideaKCM16(in[3] key[3] tmp = t[1] t[3] tmp = ideaKCM16(tmp , key[4] t[7] tmp (t[2] t[4] t[8] = ideaKCM16(t[7] key[5] tmp = t[8] tmp) out[0] t[1] t[8] out[3] t[4] tmp; tmp = tmp t[2] out[1] t[3] t[8] out[2] tmp; The resulting (see Table II) stream architecture with 14 arithmetic units and 8 automatically generated and scheduled FIFO bu#ers is shown in ....

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P. Bellows, B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, M. Rytting, A CAD Suite for HighPerformance FPGA Design, Proc. IEEE Symposium on FieldProgrammable Custom Computing Machines (FCCM), pp.1224, Apr. '99, IEEE CS '99.

....the wire interconnections are much more predictable. We are also studying the targeting for the emerging back ends constituted by debuggers, simulators and circuit generators with the capability of targeting various FPGA families. One of these new environments is supported by the Java technology [28]. Such a back end can be targeted by our compiler just by adding the capability to translate the hardware graphs to JHDL [28] Acknowledgements This work has been partially supported by the PRAXIS XXI Program under the scope of Project PRAXIS 2 2.1 TIT 1643 95. The authors would also like to ....

....by debuggers, simulators and circuit generators with the capability of targeting various FPGA families. One of these new environments is supported by the Java technology [28] Such a back end can be targeted by our compiler just by adding the capability to translate the hardware graphs to JHDL [28]. Acknowledgements This work has been partially supported by the PRAXIS XXI Program under the scope of Project PRAXIS 2 2.1 TIT 1643 95. The authors would also like to acknowledge the Portuguese PhD program of the PRODEP 5.2 action. ....

Brad Hutchings et al, "A CAD Suite for High-Performance FPGA Design," In 7 th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'99), Napa Valley, CA, USA, April 21-23, Kenneth Pocek and Jeffrey Arnold Edt., IEEE Computer Society Press (in Press).

....pool of potential users of CCMs, but mapping applications to hardware with these tools is not completely automated and still requires significant technical expertise. There have been successful efforts to create tool suites specifically designed for implementing designs on CCM architecture (e.g. [31] and [32] This type of system provides powerful tools to help the hardware designer create and test designs on CCMs. They are intended for technical users, however, and aim more at increasing the efficiency of the users, rather than widening the pool of potential users. Their primary goal is not ....

B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A CAD Suite for High-Performance FPGA Design," in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, 1999.

....not all designers can be intimately familiar with every reconfigurable architecture, some design tools abstract the specifics of the target architecture. Creating a circuit using a structural design language involves describing a circuit using building blocks such as gates, flip flops and latches [Bellows98, Gehring98, Hutchings99]. The compiler then maps these modules to one or more basic components of the architecture of the reconfigurable system. Structural VHDL is one example of this type of programming, and commercial tools are available for compiling from this language into vendor specific FPGAs [Synplicity99] ....

....from the design of general hardware circuits. For these structures, simulation and debugging are critical not only to ensure proper circuit operation, but also to prevent possible incorrect connections from causing a short within the circuit, which can damage the reconfigurable hardware. JHDL [Bellows98, Hutchings99] provides several methods of observing the behavior of a configuration during simulation. The contents of memory structures within the design can be viewed, modified, or saved. This allows on the fly customization of the simulated execution environment of the reconfigurable hardware, as well as a ....

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B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, M. Rytting, "A CAD Suite for High-Performance FPGA Design", IEEE Symposium on Field-Programmable Custom Computing Machines, 1999.

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B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting. A CAD suite for high-performance FPGA design. In Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 12--24, Napa, CA, April 1999. IEEE Computer Society, IEEE.

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B. L. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A CAD suite for high-performance FPGA design", in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, J. M. Arnold and K. L. Pocek, Eds., Napa, CA, April 1999, IEEE Computer Society, pp. 12--24, IEEE Computer Society Press.

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B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A cad suite for high-performance fpga design", in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, K. L. Pocek and J. M. Arnold, Eds., Napa, CA, April 1999, IEEE Computer Society, p. n/a, IEEE.

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B. L. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting. A CAD suite for highperformance FPGA design. In J. M. Arnold and K. L. Pocek, editors, Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 12--24, Napa, CA, April 1999. IEEE Computer Society, IEEE Computer Society Press.

.... and Brent Nelson Department of Electrical and Computer Engineering Brigham Young University 459 CB, Provo, UT 84602 grahamp ee.byu.edu, hutch ee.byu.edu, nelson ee.byu.edu Abstract While creating CCM platform independent, devicespecific readback support for hardware debugging in the JHDL [1, 2] design environment, we have found that knowing how design elements from the user s logical design were mapped to their counterparts in the FPGA physical implementation can be very useful and important. With only a partial mapping from the logical to the physical, we would not be able to provide ....

B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A cad suite for highperformance fpga design," in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines (K. L. Pocek and J. M. Arnold, eds.), (Napa, CA), p. n/a, IEEE Computer Society, IEEE, April 1999.

....before a netlist is created and processed through the FPGA implementation tools. Note that the design source itself has not changed but that the logical design database has been manipulated to include the logic analyzer before the netlist is created. We have used similar techniques within JHDL[10, 11] to instrument designs with scan chains[9] directly modifying the JHDL data structures before a design netlist has been created. The next form in the design flow is the design Netlist, a structural description of the design expressed in an FPGA vendor s design library. Design reimplementation at ....

....to connect user signals to the logic analyzer inputs and reduced potential critical path delays in the system. 4.1.2 The JHDL Demonstration System The system we created to test bitstream instrumentation for debugging was based on three main software technologies: JHDL, JBits, and JRoute. JHDL [10, 11] was developed at BYU, thus, it was relatively easy for us to modify the internal JHDL data structures to insert the logic analyzers into a user s design prior to netlisting. In addition it was relatively easy for us to modify the internal JHDL data structures to reflect changes made to the ....

B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A CAD suite for highperformance FPGA design," in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines (K. L. Pocek and J. M. Arnold, eds.), (Napa, CA), pp. 12--24, IEEE Computer Society, IEEE, April 1999.

....1.97 EBF 2216 67 0 1775 2658 3413 1.92 3445 1.30 LPBF 738 1935 30 14559 14719 24245 1.67 24391 1.66 CDI 4478 40 18 5738 6675 12812 2.23 13434 2.01 SQ 4890 3658 0 11806 14087 32192 2.73 32192 2.29 averages 2.30 1.84 3. 1 Scan Costs for Sample Designs Consider the scan overheads of several JHDL[2, 8] designs, as shown in Table 1. The first three designs are basic JHDL library modules a 4 bit up counter; a 16bit by 16 bit, fully pipelined array multiplier for which only the upper 16 bits of the product are used; and a 16 bit, fully pipelined rotational CORDIC unit. The other four circuits ....

B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting. A CAD suite for high-performance FPGA design. In K. L. Pocek and J. M. Arnold, editors, Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, pages 12--24, Napa, CA, April 1999. IEEE Computer Society, IEEE.

....Clearly, the interface provides little more than a software interface between the JBits environment and existing board capabilities and APIs, thus, the board and supporting board API must provide this functionality in some way for XHWIF to be useful. 44 Chapter 4 JHDL and Debugging JHDL[34, 35, 36] has been instrumental in experimenting with the various debugging techniques described in this work. To begin with, this chapter will describe the basic features that a design environment must provide to support the debugging techniques and mechanisms described in this dissertation. With this ....

....architecture families supported by the JHDL design API, the designer does not have to define the behavior of circuit primitives as in the examples above. Generally, the designer can either directly instance circuit elements from JHDL s FPGAspecific libraries or use the more portable JHDL Logic API[35] to describe circuits. Regarding the first option, the JHDL environment provides a collection of FPGAspecific libraries which are described using JHDL APIs and provide access to most of the design primitives recognized by the FPGA vendors tools. Designers familiar with an FPGA vendor s library ....

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B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A CAD suite for high-performance FPGA design", in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines, K. L. Pocek and J. M. Arnold, Eds., Napa, CA, April 1999, IEEE Computer Society, pp. 12--24, IEEE.

....finite field computational circuits. We have conducted an extensive survey of finite field multiplier designs and have characterized their performance on an FPGA. For each design, we created a hardware description using the Brigham Young University developed hardware description language JHDL [11]. This language easily allows us to model, simulate, and netlist our multiplier designs. Using JHDL, we verified the correct operation of each design and created an associated netlist. There were seven designs in all. 3.1 Linear Feedback Shift Register Multiplier The Linear Feedback Shift ....

B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting. A CAD suite for high-performance FPGA design. In K. Pocek and J. Arnold, editors, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 99), page TBA. IEEE Computer Society, IEEE Computer, April 1999.

....of Xilinx XC4000 circuits created with JHDL and how this mapping and FPGA state sampling, or readback, enables us to provide a hardware debugging environment with complete visibility of all flip flops and LUT RAMs in executing hardware. 1 Introduction In supporting hardware debugging in the JHDL [1, 2] design environment, we have found that knowing how design elements from the user s logical design were mapped to their counterparts in the FPGA physical implementation is quite important. With only a partial mapping from the logical to the physical, we would not be able to provide users of JHDL ....

....vendors. As a result of this and the limited logical to physical mapping used by many CCM hardware debugging environments, some correspondences between the HDL design and its physical implementation must be made manually by an experienced designer. 3 JHDL and Hardware Execution As discussed in [2], the JHDL design, simulation, and execution environment provides a unified view of a design s simulation and hardware execution they look the same in the various design views. During simulation, the simulator itself is responsible for keeping track of the values and state of the circuit ....

[Article contains additional citation context not shown here]

B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, and M. Rytting, "A cad suite for highperformance fpga design," in Proceedings of the IEEE Workshop on FPGAs for Custom Computing Machines (K. L. Pocek and J. M. Arnold, eds.), (Napa, CA), p. n/a, IEEE Computer Society, IEEE, April 1999.

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Hutchings, B., Bellows, P., Hawkins, J., Hemmert, S., "A CAD Suite for High-Performance FPGA Design", Proc. IEEE Symp. on FCCM, Napa Valley (CA), 1999

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Hutchings B., Bellows P., Hawkins J., Hemmert, S., et al., " A CAD Suite for HighPerformance FPGA Design", Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa (CA, USA), April 1999 4.7.1, 4.7.1

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Brad Hutchings, Peter Bellows, Joseph Hawkins, Scott Hemmert, Brent Nelson, and Mike Rytting, "A CAD Suite for High-Performance FPGA Design," Proceedings of the IEEE Symposium on FieldProgrammable Custom Computing Machines, April 1999.

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B. Hutchings et al. A CAD suite for high-performance FPGA design. In IEEE Symposium on FPGAs for Custom Computing Machines, pages 12-24. IEEE Computer Society Press, 1999.

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Brad Hutchings, Peter Bellows, Joseph Hawkings, Scott Hemmert, Brent Nelson, Mike Rytting. A CAD Suite for High-Performance FPGA Design.FCCM'99.IEEE Computer Society. 1999.

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