P.J. Windley and M. Coe. Microprocessor Verification: A Tutorial. Technical Report LAL-92-10, University of Idaho, Department of Computer Science, Laboratory  Home/Search   Document Details and Download   Summary   Related Articles   Check

.... strategy, we also instantiated this scheme with a formalization of a PDP 11 like two address machine with different addressing modes [2] and proved all the optimization steps for this machine as stated in [2] to be correct [5] In addition, we instantiated the generic scheme with the Tamarack [17] micro processor and verified peephole optimization rules for this processor. In [5] however, we used an older version of PVS which did not provide powerful builtin proof strategies such as GRIND. There, the degree of automation was much lower, only 83 of 108 transformations from [14] could be ....

P.J. Windley and M. Coe. Microprocessor Verification: A Tutorial. Technical Report LAL-92-10, University of Idaho, Department of Computer Science, Laboratory

....engineers and beginning CS students may find it easiest to see a microprocessor as a macro instruction interpreter, while hardware design engineers see it more concretely as a set of transistors. Windley [Win90] gives a method for hierarchical decompositions of microprocessor specifications. Coe [CW94] builds on this with four specific levels of abstraction for microprocessors, which simplifies his verification by doing it in three small steps rather than in a single, complex step. Melham [Mel89] names four types of abstraction: by its structure, by its behavior, by the data it handles, or by ....

Michael L. Coe and Phillip J. Windley. Microprocessor verification: A tutorial. Technical Report LAL-92-10, Laborator for Applied Logic, March 1994.

....level (sync i) until the temporal abstraction predicate is true (equiv (abstr i) s) then compare the two final states 5 Experimental Results 5. 1 Application to Tamarack 3 Tamarack 3 is a benchmark microprocessor described in [9, 12, 19, 22] Our specification follows the one given in [6] using HOL. We have specified Tamarack 3 at four levels: the macro level which is the assembly level, the micro level which is the microinstruction level, the phase level which is the decomposition of the micro level for each clock phase and the EBM which is the structural description ....

M. L. Coe and P. J. Windley. Microprocessor verification: A tutorial. Technical Report LAL-92-10, Laboratory for Applied Logic, Brigham Young University, Provo, Utah, 1992.

....away the fact that multiple instructions are executing simultaneously. We then verify the general behavior of the machine assuming that the instructions execute in sequence. This is much easier than proving the correctness of a program where each instruction takes many stages to execute. In [4], Coe explains a general interpreter theory, which divides verification of the Tamarack microprocessor into 3 separate proofs. He begins by specifying Tamarack at 4 levels of abstraction: the electronic block model (EBM) the phase model, the microcode model, and the macrocode model. He then ....

....and verify a microprocessor, with and without these tools. To test this thesis, we must verify a complex device whose behavior can be viewed on more than one level of abstraction; microprocessors make good subjects for this study. Verified microprocessors already exist, such as Tamarack [8] [4]. I will verify a microprocessor design twice once using the RTL tools and once without, to compare the total verification efforts. I hope to show that it s much easier to verify a design in multiple steps of abstraction using an RTL. Another artifact of this thesis will be a simulator for the ....

Michael L. Coe and Phillip J. Windley. Microprocessor verification: A tutorial. Technical Report LAL-92-10, Laborator for Applied Logic, March 1994.

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