A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement", IEEE Trans. on CAD,18(9), Sept. 1999, pp. 1265-1278. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
RPack: Routability-Driven packing for cluster-based FPGAs - Bozorgzadeh, Memik.. (2001) (1 citation) (Correct)
....denotes the number of nets with i terminals and ci is the routability weight of nets with i terminals. A net with more number of terminals is harder to route. The routability weight, ci, reflects the degree of difficulty to route a specific net with i terminals. Studies on wirelength estimation, [7], suggest that the ratio of ai, i should be chosen such that, as the number of terminals increases ci should increase. On the other hand, for high fanout nets the routability does not vary significantly. Therefore the difference of their corresponding Oti should be small. Due to this reason the ....
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, A. Ze- likovsky, "On Wirelength Estimations for Row-Based Placement," International Symposium on Physical Design, 1998.
Effective Partition-Driven Placement with Simultaneous Level.. - Zhong, Dutt (2000) (3 citations) (Correct)
....4: SLP algorithm used in SPADE: Simultaneous partitioning of multiple regions with global wire length reduction in a level of the partitioning tree. Hence, we introduce cost and gain measures based directly on halfperimeter wire length, which has been shown to be a good estimate of wire length [5]. Also, at the end of each level of processing, we recompute the width of each newly generated child region as the total size of cells contained in it, and perform compaction of regions along horizontal slice lines (row based placement) This is also carried out to estimate the wire length ....
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement," IEEE Trans. on CAD, pp. 1265-1278, Vol. 18, No. 9, Sept. 1999.
RPack: Routability-Driven packing for cluster-based FPGAs - Bozorgzadeh.. (2001) (1 citation) (Correct)
....the number of nets with i terminals and ff i is the routability weight of nets with i terminals. A net with more number of terminals is harder to route. The routability weight, ff i , reflects the degree of difficulty to route a specific net with i terminals. Studies on wirelength estimation, [7], suggest that the ratio of ff imin ff imax should be chosen such that, as the number of terminals increases ff i should increase. On the other hand, for high fanout nets the routability does not vary significantly. Therefore the difference of their corresponding ff i should be small. Due to ....
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, A. Zelikovsky, " On Wirelength Estimations for Row-Based Placement," International Symposium on Physical Design, 1998.
Rent's Rule - Coincidence or the Result of the Design Process? - Stroobandt (Correct)
....results. A new routing is then performed and so on. In order to fasten the iteration process and to improve the placement and routing results, it is mandatory to efficiently use estimates of area, wire length, etc. Three kinds of estimates are used: a priori, on line, and a posteriori estimates [1, 2]. The first kind estimates circuit parameters before any of the layout steps (floorplanning, placement, or routing) is performed. On line estimates are obtained during the layout process and are based on the information that results from the layout process itself. A posteriori estimates are ....
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky. On wirelength estimations for row-based placement. In Proc. of the 1998 Intl. Symp. on Physical Design. ACM Press, 1998.
Pre-Layout Estimation of Individual Wire Lengths - Bodapati, Najm (2000) (3 citations) (Correct)
....cell library, and use linear regression to build a wire length model. We have also proposed a method for estimating the bounding box of nets with large fanouts (more than 7) which we use to estimate their wire length. Several methods have been proposed to estimate the bounding box of a net. In [6] the authors have given a brief overview of several such methods, and have proposed a net bounding box estimation based on a Uniform Pin Distribution Model. We have used net neighborhood analysis to estimate the bounding box, and the analysis in [6] to estimate the wire lengths for nets having ....
....to estimate the bounding box of a net. In [6] the authors have given a brief overview of several such methods, and have proposed a net bounding box estimation based on a Uniform Pin Distribution Model. We have used net neighborhood analysis to estimate the bounding box, and the analysis in [6] to estimate the wire lengths for nets having large fanouts. We also show the inherent noise present in place and route tools (commercial) which makes it impossible to predict wire lengths beyond a certain accuracy. 2. METHODOLOGY The methodology used to develop the wire length model is as ....
[Article contains additional citation context not shown here]
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On wirelength estimations for rowbased placement," IEEE Transactions on ComputerAided Design, pp. 1265--1278, Sep 1999. 98
A New Heuristic for Rectilinear Steiner Trees - Ion Mandoiu Vijay (3 citations) (Correct)
....practical running times, one is immediately prompted to ask if any interest remains for sub optimal heuristics. We think that this interest will not dissapear, definitely not in RST applications where speed is more important than exact solutions, e.g. in wirelength estimation during placement [3]. Moreover, heuristics such as IRV and BI1S hold more promise than the GeoSteiner algorithm for giving efficient extensions to objective functions other than length minimization. ....
A.E. Caldwell, A.B. Kahng, S. Mantik, I.L. Markov, and A. Zelikovsky. On wirelength estimations for rowbased placement, ISPD 1998, pp. 4--11.
Min-Max Placement For Large-Scale Timing Optimization - Andrew Kahng Stefanus (2002) (4 citations) Self-citation (Kahng Mantik Markov) (Correct)
No context found.
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement", IEEE Trans. on CAD,18(9), Sept. 1999, pp. 1265-1278.
Accurate Pseudo-Constructive Wirelength and Congestion Andrew.. - Ucsd Cse And Self-citation (Kahng) (Correct)
No context found.
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement", Proc. ACM/IEEE Intl. Symp. on Physical Design, 1998, pp. 4-11.
Min-Max Placement For Large-Scale Timing Optimization - Andrew Kahng Stefanus (2002) (4 citations) Self-citation (Kahng Mantik Markov) (Correct)
No context found.
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement", IEEE Trans. on CAD, 18(9), Sept. 1999, pp. 1265-1278.
Analytical Optimization Of Signal Delays in VLSI Placement - Andrew Kahng And Self-citation (Kahng Markov) (Correct)
No context found.
A. E. Caldwell, A. B. Kahng, S. Mantik, I. Markov, A. Zelikovsky, "On Wirelength Estimations for Row-based Placement ", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.18, (no.9), IEEE, Sept. 1999
Improved Steiner Tree Approximation in Graphs - Robins, Zelikovsky (2000) (44 citations) Self-citation (Zelikovsky) (Correct)
....method. 1 Introduction Given an arbitrary weighted graph with a distinguished vertex subset, the Steiner Tree Problem asks for a minimum cost subtree spanning the distinguished vertices. Steiner trees are important in various applications such as VLSI routing [14] wirelength estimation [6], phylogenetic tree reconstruction in biology [11] and network routing [12] The Steiner Tree Problem is NP hard even in the Euclidean or rectilinear metrics [8] Arora established that Euclidean and rectilinear minimum cost Steiner trees can be efficiently approximated arbitrarily close to ....
A. Caldwell, A. Kahng, S. Mantik, I. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement", Proceedings of the International Symposium on Physical Design, Monterey, California (1998), pp. 4--11.
Toward Better Wireload Models in the Presence of Obstacles - Cheng, Kahng, Liu.. (2001) Self-citation (Kahng) (Correct)
....of This work was supported in part by the MARCO Gigascale Silicon Research Center and a grant from Cadence Design Systems, Inc. terminals [9] 1 The aspect ratio of the region or net bounding box is found to have a considerable effect on the expected wirelength for nets with few terminals [8]. All of these papers are based on regularly placed circuits such as gate arrays or standard cell designs, with the exception of [9] which considers a building block design methodology. With the trend toward IP block based System on Chip (SOC) design, it is more likely that the presence of macro ....
....region. They also create blockage by raising the cost of the route overs. 3 The wire length could also be defined as the length of the minimum spanning tree or another length, depending on the actual router. A lookup table of Steiner minimum tree lengths is presented in [9] and extended in [8] for a rectangular area of arbitrary aspect ratio. LR LB N M W H p1 p2 Fig. 1. Blocked wirelength L B versus non blocked wirelength L R in the presence of an obstacle with width W and height H in an N by M region. change L r (n) the change in wirelength due to redistribution) is given ....
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and Alex Zelikovsky, "On Wirelength Estimations for Row-Based Placement", International Symposium on Physical Design(ISPD), 1998, pp.4-11.
Design Technology Productivity in the DSM Era - Andrew Kahng Uc Self-citation (Kahng) (Correct)
....constraints well. For example, if a local routing resource has been used by a noise sensitive global bus, the back end must work around this. 5) Since there is always a chicken egg problem for top down planning, estimators that drive initial synthesis and budgeting must always be improved (e.g. [6, 11]) The high level observation is that future methodology variants require push button back end SP R. Thus, the most interesting implication of back end design convergence is that synthesis, place and route along with such supporting technology as extraction and static timing analysis ....
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement", IEEE Trans. on ComputerAided Design, Vol. 18(9), 1999, pp. 1265-1278.
Improved Steiner Tree Approximation in Graphs - Robins, Zelikovsky (2000) (44 citations) Self-citation (Zelikovsky) (Correct)
....method. 1 Introduction Given an arbitrary weighted graph with a distinguished vertex subset, the Steiner Tree Problem asks for a minimum cost subtree spanning the distinguished vertices. Steiner trees are important in various applications such as VLSI routing [13] wirelength estimation [6], phylogenetic tree reconstruction in biology [10] and network routing [11] The Steiner Tree Problem is NP hard even in the Euclidean or rectilinear metrics [8] Arora established that Euclidean and rectilinear minimum cost Steiner trees can be efficiently approximated arbitrarily close to ....
A. Caldwell, A. Kahng, S. Mantik, I. Markov and A. Zelikovsky, " On Wirelength Estimations for Row-Based Placement", Proceedings of the International Symposium on Physical Design, Monterey, California (1998), pp. 4--11.
Wire Length Prediction in Constraint Driven Placement - Liu, Hu, Marek-Sadowska (2003) (Correct)
No context found.
A.E.Caldwell, A.B.Kahng, S.Mantik, I.L.Markov and A.Zelikovsky, "On Wirelength Estimations for Row-based Placement ", IEEE Transactions on Computer-Aided Design, pp.1265-1278, Sep 1999.
Refined Single Trunk Tree: A Rectilinear Steiner Tree - Generator For Interconnect (Correct)
No context found.
A. E. Caldwell, A. B. Kahng, S. Mantic, I. L. Markov, and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement", IEEE Trans. on CAD 18(9), (1999), pp. 12651278.
Fast Floorplanning For Effective Prediction And Construction - Ranjan Bazargan Sarrafzadeh (2001) (Correct)
No context found.
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky. "On Wirelength Estimations for Row-Based Placement". In International Symposium on Physical Design, pages 4--11. ACM/SIGDA, 1998.
Sequential Delay Budgeting with Interconnect Prediction - Chao-Yang Yeh And (Correct)
No context found.
A. E. Caldwell, A. B. Kahng, S. Mantik, I.L Markow and A. Zelikovsky, "On wire length estimation for row-based placement", IEEE Trans. on Computer-Aided Design, pp. 1265-1278, Sep 1999
Partition-Driven Standard Cell Thermal Placement - Chen, Sapatnekar (2003) (2 citations) (Correct)
No context found.
A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement," IEEE Transactions on Computer-Aided Design, Vol. 18, No. 9, pp. 1265-1278, Sep 1999.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC