K. Bult and Hans Wallinger, "A class of analog CMOS circuits based on the square law characteristic of an MOS transistor in saturation," IEEE J. Solid-State Circuits, vol. SC-22, no. 3, pp. 357-365, June 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....the ART 1 m algorithm is used, instead of the 11 bit addition subtractions, we need only to realize N 11 bit subtractions, and the WTA has to choose the maximum among N 11 bit words. In the case of analog hardware, there are ways to implement the division operation with compact dedicated circuits [Bult, 1987], Snchez Sinencio, 1989] Gilbert, 1990] Sheingold, 1976] but they usually suffer from low signal to noise ratios, limited signal range, noticeable distortion, or require bipolar devices which are available for more expensive VLSI technologies. In any case, the performance of the overall ART ....

K. Bult and H. Wallinga (1987), "A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation," IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3, pp. 357-365, 1987.

....collector implant to reduce collector resistance. The collector resistance need not affect the performance of translinear circuits, so this is a viable option. However, the size of the available bipolar is substantial, and an mos current mode circuit is preferable. Such a circuit is described in [54] and is the topology we use on the foe chip. The basic three transistor core is shown in Figure 3 34. Clearly, the bias voltage V b set up by the bias current I 0 in the two transistor bias tree is V b = 2V t 2 DeltaV (3:60) where I 0 = DeltaV 2 and = C ox =2. Rearranging this, we see ....

K. Bult and H. Wallinga. A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation. IEEE Journal of Solid-State Circuits, SC--22(3):357--365, 1987.

....code for I aux . The response time of this MFC, to within 1 of the full scale output current and for input current steps greater than 0.5 A, has been estimated as less than 250ns. To provide this MFC with voltage input, the differential version of the voltage to current converter proposed in [11] has been employed. Connective circuits: Figure 4a shows the schematic of a multi input MAX circuit [12] It is used to implement a connective MIN between the rules antecedents, according to De Morgan s law: Min ( I 1 , I n ) Max ( I 1 , I n ) I ref Max ( I ref I 1 ....

K. BULT and H. WALLINGA, "A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation", IEEE Jour. of Solid-State Circuits, vol. 22, no. 3, pp. 357-365, June 1987.

....signal. The MFC used to implement equation (2) Figure 4) is described in [7] It contains three current mode D A converters to program the position (I aux ) and shape (I sat , m) of the membership functions. To also accept input signals represented by voltages, the V to I converter reported in [8] has been employed. Figure 5 shows experimental results of the fuzzification stage in our prototype. They illustrate different ways of covering the input universe of discourse by changing the slope of the central triangular label and the position of the extreme trapezoidal labels. Connective ....

K. Bult, H. Wallinga, "A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation", IEEE J. of Solid-State Circuits, Vol. 22 (3), June 1987, pp. 357-365.

....the function I out = v u u t n X i=1 I 2 i (5) for the n dimensional vector of bi directional currents I 1 ; I n . However, for vectorquantisation, the square root operation is superfluous, and the circuit can be reduced to the current squarer proposed by Bult and Wallinga [11] (figure 2) To use this circuit to calculate Euclidean distances, input currents must generated which represent the distance between two points. Hence, to calculate the distance between two vectors x and y, current inputs must be generated such that I i (x i Gamma y i ) 6) FIGURE 3 These ....

K. Bult and H. Wallinga. A class of analog CMOS circuits based on the squarelaw characteristic on a MOS transistor in saturation. IEEE Journal of Solid-state Circuits, SC-22(3), June 1987.

....antecedents and consequents of its rule base. An example is the 2.4 m CMOS prototype whose die photograph is shown in Figure 5a. This chip has two inputs that can be represented by voltages (Vx, Vy) or currents (Ix, Iy) because the MFC s previously described contain the V I converter proposed in [9]. The input spaces are covered by three fuzzy sets (N, Z, P) whose membership functions (which are symmetrical) are defined by 8 bit digital words: 5 bits, a 0 a 1 a 2 a 3 a 4 , for the position and 3 bits, b 0 b 1 b 2 , for the slopes. This means that the MFC s contain a 5 bit ....

Bult, K. and Wallinga, H., "A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation", IEEE Jour. of Solid-State Circuits, vol. 22, no. 3, pp. 357-365, June 1987.

....of a MOS transistor can be varied by changing the biasing point) Moreover, transconductance based circuits can be simple circuits with often good high frequency performance. At the MESA Research Institute at Twente University, some well known early transconductor designs have been conceived [2,3,4], as well as current gaincells [5,6,7] The design of transconductors and circuits exploiting transconductors has been a continuous research activity ever since. A recently published PhD thesis deals with transconductor design in submicron IC processes [8] and another one with the systematic ....

K. Bult , H. Wallinga, "A class of analog CMOS circuits based on the square-law characteristic of a MOS transistor in saturation", IEEE Journal of Solid-State Circuits, Vol. 22, No. 3, pp. 357-365, June 1987.

....obtained from a transistor ladder (with W L values scaled by a factor of 2) on which transistors are selected depending on the value associated to the corresponding synaptic weight bits. Once the substraction has been performed, the output current can be squared using the cells presented in [9]. There have been several proposals for implementing the analog digital multiplication scheme (see [10] for instance) but the very limited dynamic range makes them suitable only for very specific applications. In order to allow for a larger dynamic range, we have adopted a different alternative. ....

K. Bult, H. Wallinga, "A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation", IEEE Journal of Solid State Circuits, Vol. 22, No. 3, pps. 357-365, 1987.

....operations depends widely on the transistor employed and its region of operation. Circuits based on the square law characteristic of MOS transistors in saturation have been specially studied since they are compatible with standard digital technologies and can achieve a high dynamic range and speed [2]. Of particular interest are those circuits which involves the four transistor translinear loops of Fig. 1 [3] Square dividers [2] and square rooting circuits [4, 5] have been proposed based on the cell in Fig. 1a, and more elaborate structures have been designed combining these squaring circuits ....

....MOS transistors in saturation have been specially studied since they are compatible with standard digital technologies and can achieve a high dynamic range and speed [2] Of particular interest are those circuits which involves the four transistor translinear loops of Fig. 1 [3] Square dividers [2] and square rooting circuits [4, 5] have been proposed based on the cell in Fig. 1a, and more elaborate structures have been designed combining these squaring circuits [2, 6] A drawback of the structure in Fig. 1a is that floating wells must be used to remove the body effect. On one hand, this ....

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BULT, K. and WALLINGA, H.: "A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation", IEEE Trans., June 1987, SC-22, (3), pp. 357-365

.... V GS2 2V T ) 2 (5) where the different parameters have their usual meaning. If the two transistors are biased in such a way that (V GS1 V GS2 2V T ) 2 =2I B b, the combination of the former expressions gives a quadratic relation between the sum and the difference of currents, as proposed in [9]. There and also in [10] the combination of two of these squarer circuits is proposed to obtain a current multiplier divider circuit (Fig. 3a) According to expression (5) a voltage input currentoutput multiplier is obtained from the combination of two output S i 1 = R w h i C , i ( f C ....

K. Bult, H. Wallinga, "A class of analog CMOS circuits based on the square-law characteristic of an Mos transistor in saturation", IEEE SC-22, No 3, pp. 357-365, (1987).

....codes for I aux . Figure 10d shows the test obtained with the same codes in I aux but with different codes for I sat and m, resulting in a family of 8 trapezoidal functions. To provide this MFC with voltage input, the differential version of the voltage to current converter proposed in [41] can be employed. VI. CONNECTIVE STAGE Min and max operators are typical connectives. In fact, only one of them is required since they are related via De Morgan s law as follows: min ( x i ) max ( x i ) x ref max ( x ref x i ) 10) Connecting the MFC s output with a min operator ....

....studied by analog designers since CMOS transistors are inherently nonlinear devices. For a survey on this topic, the authors refer to Chapter 5 in [17] The most simple approach for a linearization technique is to combine two perfectly matched transistors operating in saturation or triode region [17, 41]. However, the resulting gain variable elements are not easily controlled, which is a problem for our purpose. This was overcome by resorting to the use of four matched transistors, connected as shown in Figure 17. This cell provides a variety of solutions for divider circuits, depending on the ....

K. Bult and H. Wallinga, "A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation", IEEE Jour. of Solid-State Circuits, vol. 22, no. 3, pp. 357-365, June 1987.

....of the circuit is shown in Figure 2b. The active area is 0.07 mm 2 in a 1.5 m CMOS technology. Figure 2c shows the experimental results obtained by programming the slope value m. To provide this MFC with voltage input, the differential version of the voltage to current converter proposed in [5] has been employed. Connective circuits: Based on the structure proposed by the authors in [6] Figure 3a) a 3 input Max circuit has been integrated in a 2.4 m CMOS technology. It is shown in the microphotograph of Figure 3b. Precision of 0.23 of the total output current (with a typical range ....

K. Bult and H. Wallinga, "A Class of Analog CMOS Circuits Based on the Square-Law Characteristic of an MOS Transistor in Saturation", IEEE Journal of Solid-State Circuits, Vol. 22, No. 3, pp. 357-365, June 1987.

....1 will be detailed in the next Sections. III. MEMBERSHIP FUNCTION CIRCUITS A simple manner to implement a Membership Function Circuit is shown in Figure 2. Inputs are voltages and outputs are currents. The input part is a voltage to current converter designed by means of a circuit described in [4]. We use PMOS transistors for a positive slope of the voltage current relationship, avoiding the substrate effect of transistor M2. Figure 2 a depicts a circuit schematic for the MFC for a triangle shaped function. Figure 2 b plots the simulated transfer characteristic for the circuit in Figure ....

K. Bult, H. Wallinga, "A class of analog Cmos circuits based on the square-law characteristic of an Mos transistor in saturation", IEEE SC-22, No 3. June 1987.

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K. Bult and Hans Wallinger, "A class of analog CMOS circuits based on the square law characteristic of an MOS transistor in saturation," IEEE J. Solid-State Circuits, vol. SC-22, no. 3, pp. 357-365, June 1987.

No context found.

K. Bult and H. Wallinga, "A class of analog CMOS circuits based on the square-law characteristic of an MOS transistors in saturation," IEEE J. Solid-State Circuits, vol. 22, pp. 357--365, June 1987.

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