R. K. Gupta, C. N. Coehlo, and G. De Micheli, "Program implementation schemes for hardware--software system," IEEE Comput., Mag., vol. 27, no. 1, pp. 48--55, 1991.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....of the approach. II. PRELIMINARIES A. Previous Work 1) Software Synthesis: Previous approaches to automated software synthesis for reactive real time systems have started either from synchronous programming languages (e.g. Esterel, 8] or from other high level languages ( 14] and [17]) In the first case, the main problem is the identification of a single FSM equivalent to the Esterel specification, and its efficient implementation as a software program. Previous versions of the Esterel compiler (v3) produced a single FSM, which resulted in a very fast implementation (as all ....

....for each CFSM; b) scheduling of CFSM transitions to satisfy timing constraints. Thus, we can take advantage of the large body of research about scheduling for real time systems (e.g. 24] for the second step. On the other hand, some of the fine grained scheduling algorithms described in [17] and [14] for example, can also be used to perform a preliminary optimization before our synthesis algorithm. This would allow an easier satisfaction of short term timing constraints (e.g. those dictated by a specific interface protocol implemented directly in software) which may be more ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli, "Program implementation schemes for hardware-software systems," IEEE Comput., vol. 27, pp. 48--55, Jan. 1994.

....several video and image processing examples. 1. 0 Motivation and Related Work System level design and behavioral transformations have been rapidly establishing themselves as key design steps wifl file most influential impact on key final performauce metrics, throughput and latency, of a design [Gup94, Wo194, Pot94a] While current system level methods and CAD tools target a variety of application domains, such as hard real time systems, embedded systems, and control applications, it is more and more apparent that DSP, and in particular image and video processing, applications are the most ....

R.K. Gupta, C.N. Coehlo, G. De Micheli, "Program Implementation Schemes for Hardware-Software System ", IEEE Computer, Vol. 27, No. 1, pp. 48-55, 1991

.... annealing Luk [105] Ruby (HDL) operation rate matching hand hierarchy Steinhausen [106] CDFG (HDL, C) operation profiling hand Ben Ismail [107] communicating task hand processes Antoniazzi [108] FSMs task hand Chou [96] timing diagram operation time (SW) min cut area (HW) Gupta [56] [109] CDFG (HDL) operation time heuristic favors software solutions. Barros et al. 100] use a graph based fine grained representation, with each unit corresponding to a simple statement in the Unity specification language. They cluster units according to a variety of sometimes vague criteria: ....

....to support memory mapped I O. The output of the algorithm is a netlist of hardware components, initialization routines and I O driver routines that can be called by the software generation procedure whenever a communication between software and hardware must take place. Gupta et al. 56] [109] started their work on software synthesis and scheduling by analyzing various implementation techniques for embedded software. Their specification model is a set of threads, extracted from a Control and DataFlow Graph (CDFG) derived from a C like HDL called Hardware C. Threads are concurrent ....

[Article contains additional citation context not shown here]

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli, "Program implementation schemes for hardware-software systems," IEEE Computer, pp. 48--55, Jan. 1994.

....in design automation techniques for system production are increasing more slowly than those of integration capabilities of ASICs. Consequently, there is a strong interest in higher levels for system modeling and synthesis and particularly hardware software codesign approaches ( 11] 7] 18] [9] for example) Starting from a high level specification of a system, codesign techniques attempt to quickly find refined specifications of effective mixed implementations by a systematic exploration of various trade offs. Codesign generally comprises several tasks including HW SW partitioning and ....

GUPTA R.K., COELHO C.N., De MICHELI G. Program implementation schemes for hardware software systems. IEEE Computer Journal. 48-55, january, 1994.

....De Micheli s group at Stanford University developed at early 90s the Olympus Synthesis System for HLS [20] and then this became part of the Vulcan 1 framework. The problem has been clearly formulated [33] and a description of the target architecture addressed by this group can be found in [31], which its by itself an extension of [33] Specifications are given in HardwareC [41] a HDL developed in Stanford University by late 80s, and then compiled into a sequencing graph model (SGM) 35] a graph representation based on flow graphs [19] using the program Hercules [42] The system ....

R. K. Gupta, N. C. Claudionor, Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, 27(1):48--55, Jan. 1994.

.... An important point was generally the description of both hardware and software using the same language, like for instance Vhdl enhanced with mechanisms for calling C functions [14] or high level languages like C, C or Fortran extended with facilities for the description of hardware systems [10]. These approaches enable the programming of both the hardware and software parts of a system in a unique framework and their validation by simulation. However, they cannot guarantee system correctness. This aspect can be much improved by using formal languages for system specification, refinement ....

Gupta R.K., Coelho C.N., De Micheli G.: "Program Implementation Schemes for Hardware-Software Systems" Computer, January 1994, pp. 48-55

....as a program, dedicated application specific integrated circuits (ASICs) are needed for performance reasons. In this context, the recent improvements in ASIC synthesis and the proliferation of advanced and inexpensive processors have stimulated interest in hardware software codesign [18, 11]. The ideal way to go about developing a new system design should then be to start with an abstract notation such that each component or module is independent of its original realization in hardware or software. The partitioning between hardware and software, using such a codesign approach, could ....

R. Gupta, C.N. Coedho, and G. De Micheli. Program implementation schemes for hardware-software systems. Computer, 48--55, January 1994. 17

....safety, select a specific application, i.e. an autonomous, intelligent cruise controller, and propose model based techniques for a realization of such a device. 2. Model based codesign A multitude of codesign techniques and methodologies are employed in academic and commercial environments [7,8,9,12,18,19]. A common trend appears to be emerging in which a clear shift in design and development paradigms is occurring. Initial approaches would foster immediate partitioning into hardware (HW) and software (SW) components, pursue HW and SW development threads in isolation from each other, and often ....

R. K. Gupta, N.C. Coelho Jr., and G. De Micheli. Program Implementation Schemes for HardwareSoftware Systems, IEEE Computer, 27(1), 48-55, 1994.

.... (see, e.g. 15] Code synthesis for control dominated applications, in which rapid reaction to external events and complex decision mechanisms dominate over pure data computations, require software or hardware to be efficiently synthesized from Finite State machine like specifications [3, 13, 9, 8]. The aim of this paper is to exploit don t care (DC) information (coming, e.g. from impossible or irrelevant conditions limited controllability) in software code synthesis. The use of DCs, to the best of our knowledge, has been limited so far only to hardware synthesis [11] Note that some ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program Implementation Schemes for Hardware-software Systems. IEEE Computer, pp. 48-55, January 1994.-

.... must support the designer during the whole development of the design (that is, from the specification of the requirements to the implementation of the modules that form the system and the corresponding communication interfaces) Several design methodologies have been proposed in literature [Gupta et al. 1994] [Chou et al. 1995] Heish et al. 1997] In general, they agree on the presence of a specification phase, a partitioning phase, and a synthesis phase. One of the fundamental aspects of any CoDesign methodologies is the technique used to define the requirements of the system,because it affects the ....

....of unbounded delay values. Another model used for the specification of systems is the Control Data Flow Graph (CDFG) The model consists of nodes and arcs; nodes indicate operations, while arcs indicate relations of dependence between the nodes. Several CoDesign methodologies are based on the CDFG [Gupta et al. 1994]. The models used to describe systems also include those based on process networks, such as the networks of SDL processes [Saracco et al. 1989] and the networks of Communicating Sequential Processes (CSP) Hoare 1985] Delta 4 In the field of CoDesign several formal languages have been used, ....

[Article contains additional citation context not shown here]

Gupta, R. K., Coelho Jr, C. N., and Micheli, G. D. 1994. Program implementation schemes for Hardware-Software systems. IEEE Computer.

....) A Development Environment for the Cosynthesis of Embedded Software Hardware Systems[10] An integrated cosynthesis environment 10 Rajesh K. Gupta et al. University of Illinois at Urbana champaign Standford University ) Program Implementation Schemes for HardwareSoftware Systems[11] An approach to system cosynthesis Table 1. The Paper List for Comparison 7 No. Top Level System Specification means Implementation of Application Hardware Proposed Application Area Partitioning method 1 High level description language based on CSP[12] ASICs and offshelf hardware ....

Rajesh K. Gupta, Claudionor N. Coelho Jr., and Giovanni De Micheli, "Program Implementation Schemes for Hardware-Software systems", in IEEE Computer, Vol. 27, No. 1, January 1994, pp. 48-55.

....for real time software speci cation, such as ESTEREL ( BCG91] StateCharts ( DH89] or some modi cation of C (e.g. WDW94] have been directly or indirectly used as hardware description languages. Conversely, methods to implement hardware speci cations in software have been proposed (e.g. GJM94] Str92] Some research has focused on particular aspects of hardware software cooperation, such as design of interfaces between hardware and software components (e.g. SB92] COB92] or formal speci cation of hardware software system properties (e.g. MKP92] Our formalism, the Co design ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, pages 48-55, January 1994.

.... Luk [LW94] Ruby (HDL) operation rate matching hand hierarchy Steinhausen [SCG 93] CDFG (HDL, C) operation profiling hand Ben Ismail [IAJ94] communicating task hand processes Antoniazzi [ABFS94] FSMs task hand Chou [CWB94] timing diagram operation time (SW) area (HW) min cut Gupta [GJM94] CDFG (HDL) operation time heuristic Table 3: A comparison of partitioning methods. 42 or hardware. Uncommitted blocks are assigned to hardware or software starting from the block which has most to gain from a specific choice. The initial partition is then improved by a Kernighan and Lin like ....

....instance ( HS91] but such cases should be carefully analyzed to limit preemption to a minimum. 47 paper model interface constraint scheduling granularity algorithm Cochran [Coc92] task list none task RMA (runtime) Chou [CWB94] task list synthesized task heuristic (static) operation Gupta [GJM94] CDFG operation heuristic with look ahead (static runtime) Chiodo [CGH 94b] task list synthesized task RMA (runtime) Menez [MABC92] CDFG operation exhaustive Table 4: A comparison of software scheduling methods. Many static scheduling methods have been developed. Most somehow ....

[Article contains additional citation context not shown here]

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, pages 48--55, January 1994.

.... of choosing a processor, doing the Hardware Software partitioning and designing the different parts [Str94] In many situations an Embedded System consists of a combination of a general purpose processor and a co processor [EHB93] or as a standard programmable element together with an ASIC [GCD94] Yet another flavor of Embedded System Design is by lowering the boundary between hardware and software even further. This can be done by implementing a system in a single processor environment. Now the software functionality is implemented on a processor while it is also possible to include ....

....Hardware Software partitioning stage In the previous section we saw that it is advantageous to have an automatic tool that guides the designer through the large design space of possible HW SW partitioning configurations. To this end, tools are being developed. Examples are COSYMA [EHB93] VULCAN [GCD94] and HSPART [KO95,Kar95] A difficult part in the design process is to supply cost data on the possible implementation alternatives. To make comparisons between the different partitioning configurations the automatic tools needs data on area occupancy and latency. As this data is not available ....

Rajesh K. Gupta, Claudionor N. Coelho Jr., and Giovanni De Micheli. Program implementation schemes for hardware-software systems. Computer, pages 48-- 55, January 1994.

....In Section 3.4, coprocessor architectures for the tuple filter are discussed. 3.2 Design method 3.2. 1 Software hardware migration The acceleration of application software by migrating parts of the software into the hardware is an aspect of hardware software codesign [DM93] KAJW93] GCJDM94] Wol93] DM94b] DM94a] Software hardware migration entails the following problems [TAS93] ffl characterizing hardware and software performance ffl identifying hardware software partitions ffl transforming functional descriptions into such partitions ffl synthesizing the resulting ....

Rajesh K. Gupta, Claudionor N. Coelho Jr., and Giovanni De Micheli. Program Implementation Schemes for Hardware--Software Systems. IEEE Computer, pages 48--55, January 1994.

....within the same application system. Keywords Hardware software codesign, Communication synthesis, Protocol selection allocation, Interface generation I. INTRODUCTION Recently the synthesis community has moved toward the highest level of abstraction commonly known as the system level [4] 9] [15] [16] 20] 32] This move vas motivated by the increasing complexity of systems and by the need for a unified approach to allow the development of systems containing both hardware and software. As the level of abstraction rise some problems heretofore non existing appear [12] 38] At the system ....

....as an allocation problem aimed at selecting, from a library, a set of communication units that implement the data exchange between the subsystems. B. Previous work Most of the work in communication synthesis for codesign has focussed on interface synthesis assuming a fixed network structure [9] [15]. Only few works in codesign handle network synthesis [7] 13] 37] In [13] Gong s network synthesis is guided by the mapping of variables (shared or private) to memory (local or global) In [37] Yen create a new processing element and a bus when it is not possible to assign a process to an ....

R.K. Gupta, C.N. Coelho and G. de Michelli, Program Implementation Schemes for Hardware Software Systems, IEEE Design & Test of Computers, Vol. 27, No. 1, pp. 48-55, January 1994.

....of the approach. 2 Preliminaries 2.1 Previous Work 2.1. 1 Software Synthesis Previous approaches to automated software synthesis for reactive real time systems have started either from synchronous programming languages (e.g. Esterel, BCG91] or from other high level languages ( CWB94, GJM94] In the rst case, the main problem is the identi cation of a single FSM equivalent to the Esterel speci cation, and its ecient implementation as a software program. Previous versions of the 8 Esterel compiler (v3) produced a single FSM which resulted in a very fast implementation (as all the ....

....The di erence is that we can take advantage of the large body of research about scheduling for real time systems (e.g. LL73] for the second step. On the other hand, some of the ne grained 1 See [Ber96a] for more on composition and causality. 9 scheduling algorithms described in [GJM94, CWB94] for example, can also be used to perform a preliminary optimization before our synthesis algorithm. This would allow an easier satisfaction of short term timing constraints (e.g. those dictated by a speci c interface protocol implemented directly in software) which may be more dicult ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, pages 48-55, January 1994. 39

....A new generation of methods and tools for system design is emerging; they are able to handle the design of mixed hardware software systems starting from system level specification. These are called co design or embedded system design tools; they provide a drastic increase in the productivity [2, 5, 7, 8, 9, 12, 17, 19, 21, 22]. This gain in productivity may be used to explore several architectural solutions to improve the quality and to reduce the cost of the final design. This paper discusses the co design of an ATM network interface card (NIC) using a co design tool called Cosmos. This experiment allowed design ....

R.K. Gupta, et al., Program Implementation Schemes for Hardware Software Systems, IEEE Design & Test of Computers, Vol. 27, No. 1, pp. 48-55, January 1994.

....pipelined or concurrent implementations must be taken into account. Others (e.g. Aco92] define it as the choice of the best processor bus memory architecture that suits a given software specification. We will use the term in a different sense (common, e.g. to [SB91] GJM92c, GJM92b, GJM92a] WWD92] meaning the design of a special purpose system composed of a few Application Specific Integrated Circuits cooperating with software procedures on general purpose processors. This restricted definition is still too wide to allow a useful formalization of generally applicable ....

....Mar90a] circuits. ffl languages for real time software specification, such as ESTEREL or StateCharts , have been directly ( Ber91] or indirectly ( NVG91] used as hardware description languages. 2. Methods to implement hardware specifications in software (e.g. WWD92] GJM92c, GJM92b, GJM92a] Str92] 3. Methods to solve various particular aspects of hardware software cooperation; for example: ffl design of interfaces between hardware and software components ( SB92] COB92] ffl formal specification of hardware software system properties ( MKP92] None ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. In Proceedings of the International Workshop on Hardware-Software Codesign, September 1992.

....Kerridge [56] Code Generation Capsys [5] Chess [58] CodeSyn [64] C. Monahan, F. Brewster [70] MOVE [36] Oscar [57] PEAS 1 [2] Analysis ADAM [48] X. Hu [37] J. Gong, et al. 29] Partitioning Cosyma [21] 34] A. Kalavade , E.A. Lee [54] K.A. Olukotun, et al. 78] Tosca [3] Vulcan [32] [31]; Case Studies GPS [102] 101] Graphics Processor [67] JPEG [30] Powertrain [37] Priority Queue [35] Spread Spectrum Receiver [26] VuMan [98] Tiger Switch [120] Achieving performance requires a careful tailoring of the system structure to the requirements imposed by the algorithms [40] ....

R.K. Gupta, C.N. Coelho, and G. De Micheli. Program implementation schemes for hardware-software systems. In IEEE Computer, pages 48--55, January 1994.

....codesign. Recent advances in synthesis systems of ICs and the proliferation of advanced and inexpensive processors have prompted system architects to investigate CAD methods for systems that contain both application specific (hardware) and predesigned reprogrammable components (software) [18, 11]. Although a reprogrammable processor can implement most system functionalities as a program, dedicated ASICs are needed for performance reasons. The ideal way to go about developing a new system design should then be to start with an abstract notation independent of a hardware or a software ....

R. Gupta, C. Coedho, and G. D. Micheli. Program implementation schemes for hardware-software systems. Computer, 48--55, Jan. 1994.

....partitioning between hardware tasks (i.e. tasks realized by dedicated hardware) and software tasks (i.e. tasks mapped onto a general purpose 6 CODESIGN FOR REAL TIME VIDEO APPLICATIONS microprocessor) is addressed by many different projects on design automation. Examples include VULCAN [ 67] [ 66], Cosyma [ 47] Tosca [ 5] and the approaches by Kalavade [ 107] Olukotun, et al. 148] among others. The current version of these approaches is not suitable for designing high performance systems because a very simple target architecture is often assumed for the partitioning. In most cases ....

R.K. Gupta, C.N. Coelho, and G. De Micheli. Program implementation schemes for hardware-software systems. In IEEE Computer, pages 48--55, January 1994. 176 CODESIGN FOR REAL-TIME VIDEO APPLICATIONS

....risks. A new generation of methods and tools for system design is emerging; they are able to handle the design of mixed hardware software systems starting from systemlevel specification. These are called co design or embedded system design tools; they provide a drastic increase in the productivity [Fel97, Mic95, Gaj95, Wol94, Tho93, Hen94, Wil94, Chi96, Rom96, Gup94]. This gain in productivity may be used to explore several architectural solutions to improve the quality and to reduce the cost of the final design. This paper discusses the co design of an ATM network interface card (NIC) using a co design tool called Cosmos. This experiment allowed design ....

R.K. Gupta, C.N. Coelho, G. de Michelli, Program Implementation Schemes for Hardware Software Systems, IEEE Design & Test of Computers, Vol. 27, No. 1, pp. 48-55, January 1994.

....demonstrating the effectiveness of the approach. 2 Preliminaries 2. 1 Previous Work Previous approaches to automated code generation for reactive real time systems have started either from synchronous programming languages (e.g. Esterel, BCG91] or from other high level languages ( CWB94, GJM94] In the first case, the main problem is the identification of a single FSM equivalent to the Esterel specification, and its efficient implementation as a software program. The approach has the advantage of producing a very fast implementation (as all the internal communication between modules ....

....1. code generation for each CFSM, 2. scheduling of CFSM transitions to satisfy timing constraints. The difference is that we can take advantage of the large body of research about scheduling for real time systems (e.g. LL73] for the second step. On the other hand, some of the algorithms of [GJM94] can also be used to perform a preliminary optimization before our synthesis algorithm. This would allow an easier satisfaction of short term timing constraints (e.g. those dictated by a specific interface protocol implemented directly in software) which may be more difficult to satisfy with ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, pages 48--55, January 1994.

....demonstrating the effectiveness of the approach. 2 Preliminaries 2. 1 Previous Work Previous approaches to automated code generation for reactive real time systems have started either from synchronous programming languages (e.g. Esterel, BCG91] or from other high level languages ( CWB94, GJM94] In the first case, the main problem is the identification of a single FSM equivalent to the Esterel specification, and its efficient implementation as a software program. The approach has the advantage of producing a very fast implementation (as all the internal communication between modules ....

....1. code generation for each CFSM, 2. scheduling of CFSM transitions to satisfy timing constraints. The difference is that we can take advantage of the large body of research about scheduling for real time systems (e.g. LL73] for the second step. On the other hand, some of the algorithms of [GJM94] can also be used to perform a preliminary optimization before our synthesis algorithm. This would allow an easier satisfaction of short term timing constraints (e.g. those dictated by a specific interface protocol implemented directly in software) which may be more difficult to satisfy with ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, pages 48--55, January 1994.

....A new generation of methods and tools for system design is emerging; they are able to handle the design of mixed hardware software systems starting from system level specification. These are called co design or embedded system design tools; they provide a drastic increase in the productivity [2, 5, 7, 8, 9, 12, 17, 19, 21, 22]. This gain in productivity may be used to explore several architectural solutions to improve the quality and to reduce the cost of the final design. This paper discusses the co design of an ATM network interface card (NIC) using a co design tool called Cosmos. This experiment allowed design ....

R.K. Gupta, et al., Program Implementation Schemes for Hardware Software Systems, IEEE Design & Test of Computers, Vol. 27, No. 1, pp. 48-55, January 1994.

....such as clock and carrier synchronization may be too demanding for a programmable processor [3] In such instances, developing applicationspecific hardware modules become a necessity. Research on embedded systems design has focused on methods and tools for automatic HW SW partitioning [4] [5], 6] In [4] an algorithm is first implemented in software and its execution speed analyzed on the chosen processor architecture. If the speed requirement is not met, parts of the algorithm are moved to dedicated hardware. In [5] the algorithm is first implemented in hardware and then less ....

....focused on methods and tools for automatic HW SW partitioning [4] 5] 6] In [4] an algorithm is first implemented in software and its execution speed analyzed on the chosen processor architecture. If the speed requirement is not met, parts of the algorithm are moved to dedicated hardware. In [5], the algorithm is first implemented in hardware and then less critical parts are transferred to software. To address the issue of uncertainty in HW and SW costs, i.e. area and execution time, possibilistic methods are described in [6] The MOVE ASP synthesis addresses the embedded system design ....

R.K. Gupta, C.N. Coelho Jr., and G. de Micheli, "Program Implementation Schemes for Hardware-Software Systems," Computing Practices, pp. 48--55, Jan. 1994.

....(Universe) and abstraction of communication between different tools (Wormholes) The HPS design flow in CASTLE concentrates more on design aspects like analysis of system requirements and the generation of hardware descriptions and processor opcode. page 4 In comparison to tools like Vulcan [17][18] and Cosyma[15] a more general view on codesign is taken in the HPS design flow. Typically codesign is considered as a partitioning between so called HW and SW components, i.e. tasks which are realized by dedicated hardware and tasks which are performed by a general purpose processor. This ....

....order to decided whether or not a unit is useful in the special context of an ES design. An important aspect when designing high performance systems(HPSs) is the memory bandwidth and memory hierarchy [8] 21] 33] The issue can not be neglected as it might be done when designing small controllers [18]. The HPS design flow includes the cheetah cache simulator for analyzing the memory access behavior. The aim MPEG File ADD SUB MULT SHIFT COMP LOAD STORE LOGIC FP EXT REST RedsNightmare.mpg 22.58 0.70 0.00 25.47 25.25 6.90 3.32 15.16 0.00 0.62 0.00 anim.mpg 20.49 0.75 0.00 27.16 ....

R.K. Gupta, C.N. Coelho, G. De Micheli: "Program Implementation Schemes for Hardware-Software Systems", IEEE Computer, pp. 48-55, Jan. 1994.

....for real time software specification, such as ESTEREL ( BCG91] StateCharts ( DH89] or some modification of C (e.g. WDW94] have been directly or indirectly used as hardware description languages. Conversely, methods to implement hardware specifications in software have been proposed (e.g. GJM94] Str92] Some research has focused on particular aspects of hardware software cooperation, such as design of interfaces between hardware and software components (e.g. SB92] COB92] or formal specification of hardware software system properties (e.g. MKP92] Our formalism, the Co design ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, pages 48--55, January 1994.

No context found.

R. Gupta, C. Coelho, and G. De Micheli, "Program implementation schemes for hardware-software systems," IEEE Computer, pp. 48--55, Jan. 1994.

....of threads over time, however, depends on control and data transfers, and thus a control data driven scheduler is used in the software that allows both software and hardware to schedule threads over time. For further information on this control data driven scheduler, we refer the reader to [8, 9]. We also assume that threads will execute in a general purpose microprocessor with a single level memory hierarchy. The hardware is synthesized using synthesis tools capable of scheduling operations over time, and allocating and binding resources and registers [13] We assume here that the ....

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, pages 48 55, January 1994.

....S1, of the calling thread. That is, the variables common to 1 and 2 are only read and not modified by the loop body. In such cases the reaction rate of a program thread can be maintained by use of data buffers between program threads. For implementation details, the reader is referred to [25]. Hardware software interface Due to the serial execution of the software component a data transfer from hardware to software must be explicitly synchronized. Using a polling strategy, the software component can be designed to perform pre meditated transfers from the hardware components based on ....

R. K. Gupta, C. C. Jr., and G. D. Micheli, "Program Implementation Schemes for Hardware-Software Systems," in International Workshop on Hardware-Software Co-design, Oct. 1992.

....and executed on the standard processor and (ii) the specification of the remaining hardware circuits, that can be synthesized as a netlist of logic gates. Hardware software synchronization units for interfacing the processor to the application specific logic are also automatically generated [3, 5, 6]. Both Cosyma and Vulcan partition the system specification with a fine granularity, i.e. partition blocks are sets of operations. Conversely, the Co SAW tool suite [7] partitions systems with a coarse granularity, i.e. blocks correspond to processes. Whereas some optimality is lost in using a ....

R. Gupta and G. De Micheli, "Program Implementation Schemes for Hardware-Software Systems," IEEE Computer, Vol. 27, No. 1, pp. 48-55, January 1994.

....and most effective for local variables. These locals are defined by the storage M(G) associated with the flow graph model. 4. 5 Effect of runtime scheduler The runtime scheduler refers to the main program in software that integrates calls to various program threads implemented as coroutines [26]. As explained earlier, the runtime system used here mainly consists of a scheduler that invokes program threads at runtime. This scheduler can be of the following two types: ffl Non preemptive runtime scheduler. Here a program thread executes either to its completion or to the point when it ....

R. K. Gupta, C. Coelho, and G. D. Micheli, "Program Implementation Schemes for HardwareSoftware Systems," IEEE Computer, Jan. 1994.

....satisfiability of the imposed timing constraints. How can you determine if a valid serialization for a given set of timing constraints exists If so, how do you define and choose an optimum optimal serialization The following references detail the issue and point to some answers [CB94, GRVD87, GCM94, CGH 95] Optimization of machine code for embedded systems is a more general problem than code optimization for general purpose computing systems, due to the additional dimension of detailed timing constraints and response time requirements [Cha82, FOW87, GG90, GM94a] Hardware synthesis ....

Rajesh K. Gupta, Claudionor Coelho, and G. De Micheli. Program Implementation Schemes for Hardware-Software Systems. IEEE Computer, January 1994.

....software required to implement the scheduler. For constraint analysis purposes, it is not necessary to determine a specific schedule of operations, but only to verify the existence of a schedule. We present constraint satisfiability tests in the context of a multi threaded software implementation [7] and a bilogic relative schedule for hardware portions [8] The satisfiability tests are based on a timing constraint graph, GT = V; E; Delta) where the set of edges consists of forward and backward edges, E = Ef [Eb and ffi ij 2 Delta defines the weights on edges such that tk (v i ) ffi ij ....

....operation that iterates until the concerned input (signal) is received. This implementation is commonly used for hardware synthesis [9] In another implementation, the execution of wait operation causes a context switch. This implementation is particularly applicable for software implementations [7]. For this implementation, the delay of the wait operation is characterized by a fixed overhead as the delay due to the runtime system, and hence treated as a non ND operation. 3 Implementation Operation level constraint analysis is implemented as a part of the co synthesis framework, Vulcan ....

R. K. Gupta, C. Coelho, and G. D. Micheli, "Program Implementation Schemes for Hardware-Software Systems," IEEE Computer, Jan. 1994.

....side effect on storage, S1, of the calling thread. That is, the variables common to read and not modified by the loop body. In such cases the reaction rate of a program thread can be maintained by use of data buffers between program threads. For implementation details, the reader is referred to [25]. Hardware software interface Due to the serial execution of the software component a data transfer from hardware to software must be explicitly synchronized. Using a polling strategy, the software component can be designed to perform pre meditated transfers from the hardware components based on ....

R. K. Gupta, C. C. Jr., and G. D. Micheli, "Program Implementation Schemes for Hardware-Software Systems," in International Workshop on Hardware-Software Co-design, Oct. 1992.

No context found.

R. K. Gupta, C. N. Coehlo, and G. De Micheli, "Program implementation schemes for hardware--software system," IEEE Comput., Mag., vol. 27, no. 1, pp. 48--55, 1991.

No context found.

R.K. Gupta, C.N. Coelho and G. de Michelli, Program Implementation Schemes for HardwareSoftware Systems, IEEE Design &Test of Computers, Vol. 27, No. 1, pp. 48-55, January 1994.

No context found.

R. K. Gupta, C. N. Coelho Jr., and G. De Micheli. Program implementation schemes for hardware-software systems. IEEE Computer, pages 48--55, January 1994.

No context found.

R. K. Gupta, C. N. Coelho, Jr., and G. De Micheli, "Program implementation schemes for hardwaresoftware systems," IEEE Computer, Vol. 27, no. 1, pp. 48-55, Jan. 1994.

No context found.

R. K. Gupta and C. N. Coelho Jr., "Program Implementation Schemes for HardwareSoftware Systems", IEEE Computer, Vol. 27, No. 1, 1994, pp. 48-55.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC