| A. Gottlieb, R. Grishman, C. Kruskal, K. McAuliffe, L. Rudolph, and M. Snir. The NYU multicomputer - designing a MIMD shared-memory parallel machine. IEEE TOPLAS, 5(2):164--189, Apr. 1983. |
.... The designers of traditional multiprocessors have included hardware support only for simple operations such as compare and swap and load linked store conditional, while high level synchronization primitives such as locks, barriers, and condition variables have been implemented in software [9, 14, 15]. With the advent of directory based distributed shared memory (DSM) multiprocessors with significant flexibility in their cache controllers [7, 12, 17] it is worthwhile considering whether this flexibility should be used to support higher level synchronization primitives in hardware. In ....
....traditional multiprocessors have included hardware support only for simple operations such as test and set, fetch and op, compare and swap, and load linked store conditional. Higher level synchronization primitives such as locks, barriers, and condition variables have been implemented in software [9, 14,15]. However, these designs were all originally based on simple bus based shared memory architectures. Recent scalable shared memory designs have employed distributed directories and increasingly sophisticated and flexible node controllers [7, 12, 17] In particular, as part of maintaining data ....
A. Gottlieb, R. Grishman, C.P. Kruskal, K.P. McAuliffe, L. Rudolph, and M. Snir. The NYU multicomputer - designing a MIMD shared-memory parallel machine. IEEE Transactions on Programming Languages and Systems, 5(2):164--189, April 1983.
.... The designers of traditional multiprocessors have included hardware support only for simple operations such as compare and swap and load linked store conditional, while high level synchronization primitives such as locks, barriers, and condition variables have been implemented in software [9, 14, 15]. With the advent of directory based distributed shared memory (DSM) multiprocessors with significant flexibility in their cache controllers [7, 12, 17] it is worthwhile considering whether this flexibility should be used to support higher level synchronization primitives in hardware. In ....
....traditional multiprocessors have included hardware support only for simple operations such as test and set, fetch and op, compare and swap, and load linked store conditional. Higher level synchronization primitives such as locks, barriers, and condition variables have been implemented in software [9, 14,15]. However, these designs were all originally based on simple bus based shared memory architectures. Recent scalable shared memory designs have employed distributed directories and increasingly sophisticated and flexible node controllers [7, 12, 17] In particular, as part of maintaining data ....
A. Gottlieb, R. Grishman, C.P. Kruskal, K.P. McAuliffe, L. Rudolph, and M. Snir. The NYU multicomputer - designing a MIMD shared-memory parallel machine. IEEE Transactions on Programming Languages and Systems, 5(2):164--189, April 1983.
No context found.
A. Gottlieb, R. Grishman, C. Kruskal, K. McAuliffe, L. Rudolph, and M. Snir. The NYU multicomputer - designing a MIMD shared-memory parallel machine. IEEE TOPLAS, 5(2):164--189, Apr. 1983.
No context found.
A. Gottlieb, R. Grishman, C.P. Kruskal, K.P. McAuliffe, L. Rudolph, and M. Snir. The NYU multicomputer - designing a MIMD shared-memory parallel machine. IEEE Transactions on Programming Languages and Systems, April 1983.
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