K. M. Chu and D. L. Pulfrey, "A comparison of CMOS circuit technique: differential cascode voltage switch logic versus conventional logic," IEEE J. of Solid-State Circuits, SC-24: 779-786, 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....lookahead adder (SCLA) 1] is an asynchronous version of carry lookahead adder. The original implementation of SCLA has a problem that all primary inputs must be precharged. Recently proposed implementation in [2] solves such a problem by employing differential cascode voltage switch logic (DCVSL) [3], where nmos transistors connecting between evaluation trees and ground postpone evaluation control the evaluation. Therefore, regardless of its input values, the evaluation does not start until the start signal is valid. However, in both implementations, the completion detecting signal of each ....

....B A P = generate ( B A G = kill( B A K = a carry for each pair of input bits is shown in Fig. 4(a) For this block, previous implementations [1,2] use an XOR gate and a NAND gate. However, as shown in Fig. 4(a) such a block can be implemented efficiently using multiple output DCVSL [3]. The proposed circuit implements the same function with less transistors, which results in smaller input driving capacitance, lower power consumption, and area reduction. A circuit for a 4 bit carry chain is also implemented using multiple output DCVSL as shown in Fig. 5. The previous ....

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Chu, K. M., and Pulfrey, D. L.: `A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic', IEEE JSSC, 1987, SC-22, (4), pp. 528-532.

....cascode logic circuits in favor of traditional CMOS styles. The high activity of DCVS gates and the need to route differential signals cause them to compare unfavorably with respect to implementations using static CMOS , complementary pass transistor logic, and differential pass transistor logic [1, 2]. However DCVS gates do offer the potential of having high fan in which leads to a reduction in logic depth, high speed, and the capability of generating completion signals for asynchronous operations. We hope that the advantages of DCSL in these areas would merit a second look at these gates. 1 ....

K. M. Chu, D. L. Pulfrey, "Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic versus Conventional Logic", IEEE Journal of Sold State Circuits, vol. 22, no. 4, Aug 1987, pp. 528-532

....Area analysis: if we compare dividers with the same number of stages, the area of the asynchronous divider is twice that of the synchronous one. We explain it as follows : The DCVS logic used is a structure less regular than the standard CMOS one and so takes more area when layed out on silicon [15]. The control and detection circuit of the asynchronous divider is certainly more important than the clock and FlipFlop range circuits which represent at most 10 of the total area. Compared to a full custom design, the use of standard cells encreases the silicon area. Power dissipation ....

....FlipFlop range circuits which represent at most 10 of the total area. Compared to a full custom design, the use of standard cells encreases the silicon area. Power dissipation analysis: The DCVS logic used in the asynchronous circuit is responsible for the doubled power consumption as stated in [15], although the cells have been optimized [9] In addition to this, the clock effect has not a big influence in this circuit, because the synchronous divider is almost combinatorial and the only synchronous part is the Flip Flop range controlled by a gated clock. The use of a gated clock resolves ....

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K. M. Chu, D. L. Pulfrey " A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic ", IEEE Journal of Solid-State Circuits, Vol. sc-22, No. 4, August 1987.

....and neither solely for speed nor solely for energy. A variety of studies have been made to study the relative energy consumption and speed of various macrocells, which can be used to aid in making design decisions [32] 33] Similar studies have also been with respect to various logic design styles [34]. Transistor level optimizations can be made, such as minimizing all devices not in the critical path(s) This typically requires have a fast and slow versions of the same cell, and the cell selection is based on whether it is in the critical path(s) or not [30] Low voltage swing circuits for ....

K. Chu and D. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic," IEEE Journal of Solid State Circuits, Aug. 1987, pp. 528-32.

.... Cascode Voltage Switch Logic The differential cascode voltage switch (DCVS) logic has been the most widely used structure to design CMOS self timed circuits because its advantages over traditional NAND NOR circuit techniques in terms of delay, power dissipation, layout area and logic flexibility [15]. Some MESFET DCVS approaches have been proposed in the literature aiming at decreasing the power dissipation by increasing the gate complexity [9 11] The GaAs version closest to CMOS and perhaps the most interesting is presented by Chandramouli et al. 11] shown in Fig. 4b. The logic part ....

Chu, K.M. & Pulfrey, D.L. A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic. IEEE Journal of Solid-State Circuits. Vol. SC-22, no.4, Aug.87, pp.528-32.

....to wirelength and communication bandwidth is inversely proportional to wirelength. Massively parallel architectures need to be very careful about the number of long range connections. 10 James B. Burr year what who description Static Fully static CMOS 1982 Domino [39] Domino logic 1987 DCVSL [16] Differential cascode voltage switch logic 1987 DPTL [51] Differential pass transistor logic 1990 CPL [68] Complementary pass transistor logic 1991 L DPTL [40] Latched differential pass transistor logic Table 2: Logic design styles. 4 Building blocks A number of basic circuits and circuit ....

....The highest speed logic families also tend to consume the most power. The most compact tend to be slow. Fully static logic offers high speed, reasonably small area, and low power. Domino logic [39] offers less area but higher power, and is dynamic. Differential cascode voltage switch logic (DCVSL) [16] is popular in asynchronous design because each complex logic gate generates its own completion signal. It is quite high power, however, since every output toggles on every cycle. Complementary pass transistor logic (CPL) offers modest performance, Digital Neurochip Design 11 year what who ....

K. M. Chu and D. L. Pulfrey. A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic. IEEE Journal of Solid-State Circuits, SC-22:528--532, 1987.

....of a completion signal indicating the outputs of the logic module are valid, there is additional overhead circuitry. There are several circuit approaches to generate the requisite completion signal. One method is to use dual rail coding, which is implicit in certain logic families such as the DCVSL[13,20]. The completion signal in a combinational macrocell made up of cascading DCVSL gates consists of simply ORing the outputs of only the last gate in the chain, leading to small overhead requirements. However, for each computation, dual rail coding guarantees a switching event will occur since at ....

K. Chu and D. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Journal of Solid-State Circuits, pp. 528-532, August 1987.

....be as big as possible, while the transistor forming the latch should have to be of minimum size. Figure 10 shows the structure of a generic SRPL gate. NMOS CPL network F F Figure 10: Basic SRPL Gate. 2. 3 Differential Cascode Voltage Switch Logic (DCVSL) Differential cascode voltage switch logic [17, 7, 8], may be either static or dynamic. It is formed by a NMOS differential network where the input signals appear both in direct and complemented form and by a pair of cross coupled pull up PMOS transistors. NMOS combinational network F F Differential inputs (a) NMOS combinational network ....

K. M. Chu, D. L. Pulfrey, "A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic", IEEE Journal of Solid State Circuits, v. 22, n. 4, pp. 528---532, August 1987.

....wide range of parameters including process feature size, number and type of interconnect layers has also been characterized [6] 43] 57] Separately, both industrial and academic teams have detailed their experiences and tradeoff choices for the physical design of a wide selection of designs. 7] [17] [23] 26] 37] 40] 58] 61] 63] 65] Finally, several studies have been performed to quantify the human effort costs of various chip implementation flows [34] 35] 36] While this thesis draws from the collective experience of past work, it differs from past work primarily in three important ....

Chu, K. M., and Pulfrey, D. L. A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic. IEEE Journal of Solid State Circuits (August 1987), 528--531. CVSL, Circuit Techniques.

....cmos, design, high performance, low voltage, low power dissipation. I. INTRODUCTION Unlike conventional CMOS circuit designs which use low functionality gates with limited fan in, differential cascode voltage switch circuits (DCVS) allow much higher functionality with greater fan in [1] [2], 3] This is especially true for DCVS logic styles which use internal sense circuits (a cross coupled inverter pair) to speed output transitions, as in the case of Enable Disable Cascode voltage switch logic (ECDL) 5] 7] Sample Set Differential Logic (SSDL) 4] Latched differential cascode ....

K. M. Chu, D. L. Pulfrey, "Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic versus Conventional Logic," IEEE J. Solid State Circuits, vol. 22, no. 4, pp. 528-532, Aug 1987.

....CMOS styles. This is mainly because the high activity of DCVS gates cause them to compare unfavorably with respect to conventional CMOS implementations from a power perspective [1] The need to route differential signals, and the high clock load of clocked DCVS styles are known disadvantages [1] [2]. However this sort of logic has potential advantages as compared to standard CMOS NAND(NOR) implementations. ffl High complexity, high fan in gates are possible. Complex gates can be implemented with lower transistor count. Certain clocked DCVS families have very low propagation delay for large ....

....stage. The DCSL1 output stage of figure 4 is used. To ensure safe operation, clock to T10 in figure 4 is a delayed version of the 6 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 4.0 4.0 4.0 4.0 4.6 4.6 5.2 5. 2 DCSL Output DCSL Output CO CO A[0] A[1] A[1] A[2] A[0] A[2] A[3] A[3] S S CY CY CI CI Fig. 14. A DCSL 4 2 compressor actual clock. This DCSL output stage has 12 transistors. Hence the reduction in output stages reduces the transistor complexity significantly. A simple algorithm was used to generate the NMOS tree from the 4 2 truth table. The ....

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K. M. Chu, D. L. Pulfrey, "Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic versus Conventional Logic," IEEE J. Solid State Circuits, vol. 22, no. 4, pp. 528-532, Aug 1987.

....power dissipation. Also, the usage of dynamic gates is not as straightforward and universal as it is for static gates, and robustness is considerably degraded. With the exception of some very special circuit applications, dynamic logic is no viable candidate for low power circuit design [1] 8] [9] and was therefore not considered any further in this study. E. Complementary CMOS Logic Style Logic gates in conventional or complementary CMOS (also simply referred to as CMOS in the sequel) are built from an NMOS pull down and a dual PMOS pull up logic network. In addition, pass gates or ....

K. Chu and D. Pulfrey, "A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic", IEEE J. Solid-State Circuits, vol. 22, pp. 528--532, Aug. 1987.

....circuits. b) DCVS The differential cascode voltage switch (DCVS) logic has been the most widely used structure to design CMOS self timed circuits deu to the advantages over traditional NAND NOR circuit techniques in terms of delay, power dissipation, layout size and logic flexibility [6,13]. This structure was recently adapted to MESFET circuits by Chandramouli et al. 7] The load part was redesigned to avoid critical GaAs problems like the gate conduction of next stages and the subthreshold leakage currents of transistors connected to the precharged nodes. The GaAs DCVS structure ....

Chu, K.M. & Pulfrey, D.L. A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic. IEEE JSSC, Vol. SC-22, no.4, Aug.87, pp.528-32.

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K. M. Chu and D. L. Pulfrey, "A comparison of CMOS circuit technique: differential cascode voltage switch logic versus conventional logic," IEEE J. of Solid-State Circuits, SC-24: 779-786, 1987.

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