P Salverda. An SRAM Main Memory Model, MSc research report, University of the Witwatersrand, Johannesburg, September 1997.  Home/Search   Document Details and Download   Summary   Related Articles

....Additionally, it is desirable that context switching code be locked in the cache to avoid the situation where it calls itself recursively when part of its code causes a cache miss. One way to achieve this is to manage the lowest level of cache as a paged memory. The RAMpage memory hierarchy [Salverda 1997, Machanick et al. 1998] proposes that main memory be moved up to the lowest level of SRAM cache while DRAM is managed as a first level paging device, and the disk becomes a second level paging device. This arrangement 2 allows the necessary modifications to be made to support context switching ....

....device, and the disk becomes a second level paging device. This arrangement 2 allows the necessary modifications to be made to support context switching on DRAM accesses: SRAM misses to DRAM are handled in software and context switching code can be pinned in SRAM. RAMpage simulation results [Salverda 1997] indicate performance improvements over the standard memory hierarchy. Moreover, these improvements are shown to scale with the expected future CPU DRAM speed gap increases. Improvements come mainly from a lower SRAM miss rate, particularly when large page sizes are used. However, the benefit of a ....

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P Salverda. An SRAM Main Memory Model, MSc research report, University of the Witwatersrand, Johannesburg, September 1997.

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