Clifford W. Mercer, Stefan Savage, Hideyuki Tokuda, Processor Capacity Reserves: An Abstraction for Managing Processor Usage, in Proceedings of the IEEE Fourth Workshop on Workstation Operating Systems (WWOS-IV), 14-15 Oct. 1993, IEEE Comp. Soc. Press, pages 129-134  Home/Search   Document Details and Download   Summary   Related Articles   Check

....exhausts the CPU, other CMThreads are affected by it. To solve these problems, more system support for resource management is needed, namely, Reservation and restriction of resource use Information about resource use For the CPU resource, the processor capacity reser vation mechanism [14, 15] of RT Mach can be used. This mechanism makes available in the system a new abstraction named reserve. A reserve represents a CPU resource reservation in a form of requires (7 sec o of the CPU) As shown onds every T seconds (i.e. T in Fig. 10, every thread in the system is associated with a ....

C. W. Mercer et al.: "Processor Capacity Reserves: An Abstraction for Managing Processor Usage," Proc. th Workshop on Workstation Operating Sys- tems, pp. 129 134 (1993).

....and its schedulability verified. The main workload of the above mentioned applications is periodic in nature. Sporadic and aperiodic tasks can be treated as periodic by allotting them a periodically replenished execution budget, e.g. a deferrable server [1] or a processor capacity reserve [2]. Thus, we assume that all tasks are periodic. We propose a new workload partitioning and assignment algorithm for periodic tasks in large heterogeneous real time systems, which attempts to find an assignment of tasks to processors that results in a feasible schedule. The contributions of our ....

C. W. Mercer, S. Savage, and H. Tokuda, "Processor capacity reserves: An abstraction for managing processor usage," in WWOS, 1993. 129--134.

....right in Fig. 1. The first prototype of the QOS Ticket model is implemented on RT Mach. This experimental QOS Manager, named QOS Control Server, controls the CPU resource allocation among multiple CM Threads. As the QOS Ticket for the CPU resource, the processor capacity reservation mechanism [16, 17] of RTMach is used. This mechanism makes available in the system a new abstraction named reserve. A reserve represents a CPU resource reservation in a form of requires C seconds every T seconds (i.e. C T of the CPU) As shown in Fig. 6, every thread in the system is associated with a ....

C. W. Mercer et al.: "Processor Capacity Reserves: An Abstraction for Managing Processor Usage," Proc. 4th Workshop on Workstation Operating Systems, pp. 129--134 (1993).

....by Wulf s postmortem on HYDRA C.mmp [Wul81] EROS unifies domains of authority and processes into a single object known as a domain (Figure 2) A domain is a cgroup (known as the domain root) which contains: A schedule capability. The EROS scheduler implements processor capacity reserves [Mer93]. Schedule capabilities convey the authority for a running domain to execute instructions under a particular scheduling reserve. A keeper start capability naming the domain (the keeper) responsible for handling execution faults incurred by this domain. A segmode capability naming the address ....

Clifford W. Mercer, Stefan Savage, and Hideyuki Tokuda. "Processor Capacity Reserves: An Abstraction for Managing Processor Usage," Proceedings of the Fourth Workshop on Workstation Operating Systems (WWOSIV) , October 1993

....are incurred by a single interrupt handler thread. The inappropriate structure of microkernel based operating systems, where the majority of system services are provided by servers, introduces the need for complicated resource transfer mechanisms. The Processor Capacity Reserves scheme [Mercer93] allows processor time originally allocated to an application, in the form of a reserve to be used by a server when performing an Remote Procedure Call (RPC) There is no way to ensure, however, that the processor time is used for the purposes for which it was originally intended, and for any ....

....be used by a server when performing an Remote Procedure Call (RPC) There is no way to ensure, however, that the processor time is used for the purposes for which it was originally intended, and for any timeliness guarantees to be preserved, the server must internally schedule clients requests. [Mercer93] describes the need to modify the X Window System Server to service its clients in a prioritised fashion to maintain the QoS guarantees of video display applications. Lottery scheduling [Waldspurger94] shares the processor between a number of kernel threads using statistical mechanisms. A cheap ....

[Article contains additional citation context not shown here]

Clifford W. Mercer, Stefan Savage, and Hideyuki Tokuda. Processor Capacity Reserves: An Abstraction for Managing Processor Usage. In Proc. Fourth Workshop on Workstation Operating Systems (WWOS-IV), October 1993. (pp 21, 72)

....previous reservations, and if so, returns a capability to an appropriate kernel reserve. This reserve capability can be placed in the schedule slot of a process s root node; all processes sharing a given reserve capability will run under the named reserve. In contrast to previous implementations [Kit93, Mer93], Processor reserves are not inherited across IPC operations. Priority inheritance raises a host of protection domain violation issues if reserves are inherited, a caller might call a service and then shut off its reserve, denying service to other callers. Reserve inheritance lends itself to ....

C. W. Mercer, S. Savage and H. Tokuda. "Processor Capacity Reserves: An Abstraction for Managing Processor Usage," in Proc. 4th Workshop on Workstation Operating Systems, October 1993.

....Fawn system, allocation is based on a fixed ticker (100ms in this case) allowing no precision in scheduling below this level. Furthermore, extra time in the system is implicitly handed out equally to all domains: there is no room for a tailor able allocation policy. Processor Capacity Reserves [Mercer93] is a scheme similar to Nemesis in specifying the service required by an application in terms of processor bandwidth. However, the problem of shared servers is addressed by having clients transfer resource reservations to the server, with the server charging time to the client. This can create ....

Clifford W. Mercer, Stefan Savage, and Hideyuki Tokuda. Processor Capacity Reserves: An Abstraction for Managing Processor Usage. In Proc. Fourth Workshop on Workstation Operating Systems (WWOSIV) , October 1993. (p 69)

....provided in other areas of the system; QoS guarantees must be provided for all resources. Some systems attempt to address the problem of providing QoS for shared servers by providing resource transfer mechanisms (for example, through thread migration [Hamilton93] or processor capacity reserves [Mercer93] These schemes allow resources used by the server on behalf of the client to be accounted to the client. Unfortunately, the client must rely on the server to make scheduling decisions on its behalf, restricting its ability to have its own application speci c thread scheduling policy. In ....

....average of recent experience. These problems with priority based scheduling schemes have been identi ed by a number of groups, and have led to the development of scheduling regimes designed to support the quality of service guarantees required by soft real time applications [Coulson93, Hyden94, Mercer93, Nieh97, Jones97, Roscoe95] 2.4.2 Soft real time scheduling The Lancaster University SUMO project [Coulson93] modi ed the Chorus microkernel to add support for soft real time CPU scheduling classes. SUMO uses a split level scheduling [Govindan91] scheme, whereby application threads are not ....

[Article contains additional citation context not shown here]

Cliord W. Mercer, Stefan Savage, and Hideyuki Tokuda. Processor Capacity Reserves: An Abstraction for Managing 173 Processor Usage. In Proc. Fourth Workshop on Workstation Operating Systems (WWOS-IV), October 1993. (pp 3, 17, 26)

....is never mapped in such a way that access is permitted from user mode programs. Capability load and store instructions are emulated in supervisor software, and check the per page type tag. The kernel also implements LRU paging and the dispatch portion of a scheduler based on capacity reserves [35]. As these ideas are not new, they are not discussed further in this paper. 3.1 Address translation Like other recent microkernels, EROS views an address space as a set of mappings of the form: vpage ppage fr; wg handler where handler is an entry capability to a process (Section 3.2) ....

C. W. Mercer, S. Savage, and H. Tokuda. Processor capacity reserves: An abstraction for managing processor usage. In Proc. 4th Workshop on Workstation Operating Systems, pages 129--134, Oct. 1993.

....the CPU Power Regulator (CPR) which improves the capability of Windows NT 95 in servicing time critical applications. CPR considers a distance model [4] to service time critical applications such as multimedia softwares and electronic games in a timely fashion. Distinct from the past work [7, 8, 9], CPR adopts a user level control mechanism to manage the resource allocations on Windows NT 95 and makes no modifications to the operating system and application softwares. The performance of CPR was verified by a collection of simulation experiments of randomly generated and realistic workloads. ....

....model [4] in which each application i is serviced at a fixed interval D i , as shown in Figure 1. CPR is responsible to properly multiplex CPU cycles among applications in a periodic way. For implementation, CPR adopts a user level control mechanism based on the idea of time reservation [7, 8, 9] to multiplex CPU cycles among applications. Distinct from the past work, CPR makes no modifications to the operating system or any application program. CPR considers a model of resource reservation at the application level, which is more natural for ordinary users and better for modular design of ....

[Article contains additional citation context not shown here]

C.W. Mercer, S. Savage, and H. Tokuda, "Processor Capacity Reserves: An Abstraction of Managing Processor Usage," In Proceedings of the Fourth Workshop on Workstation Operating Systems (WWOSIV) , October 1993.

....new types of applications with conventional interactive and batch applications. Many schedulers have tried, and in part have succeeded, to address these requirements. Generally, these schedulers fall in two categories: proportional share [2, 26, 28, 29, 30] and real time 1 based schedulers [20, 21, 22]. In proportional share algorithms each client has associated a weight which determines the share of the resource that the client should receive. The scheduler tries to allocate the resource among competing clients in proportion to their share. For example, consider two clients with weights 1 and ....

....higher level resource abstractions are needed to specify the applications requirements. We note here that many of the existing abstractions, such as tickets and currencies (developed by Waldspurger and Weihl [28, 30] and processor capacity reserves (proposed by Mercer, Savage and Tokuda [20]) are easily supported by EEVDF. For example, in lottery scheduling the number of tickets held by a client could be directly translated into the weight associated to that client in the EEVDF algorithm. By efficiently implementing dynamic operations, the EEVDF provides direct support for higher ....

[Article contains additional citation context not shown here]

C. W. Mercer, S. Savage, and H. Tokuda "Processor Capacity Reserves: An Abstraction for Managing Processor Usage", Proc. of the Fourth Workshop on Workstation Operating Systems, October 1993

....on its importance; tasks with shorter periods are always assigned higher priorities. Another common technique is earliest deadline scheduling [LL73] which always schedules the task with the closest deadline first. Higher level abstractions based on real time scheduling have also been developed [MST93, MST94] However, realtime schedulers generally depend upon very restrictive assumptions, such as precise static knowledge of task execution times and prohibitions on task interactions. Strict limits are also placed on processor utilization, so that even transient overloads are disallowed. A ....

....and modularity properties, requiring low level information such as task execution times to be globally exposed. However, it is possible to layer higher level abstractions on top of a realtime scheduling substrate. Mercer, Savage, and Tokuda have developed a processor capacity reserve abstraction [MST93, MST94] for measuring and controlling processor usage in a microkernel system with an underlying real time scheduler. Reserves can be passed across protection boundaries during interprocess communication, with an effect similar to the use of ticket transfers. While this approach works well for ....

Clifford W. Mercer, Stephan Savage, and Hideyuki Tokuda. Processor capacity reserves: An abstraction for managing processor usage. In Proceedings of the Fourth Workshop on Workstation Operating Systems (WWOS), pages 129--134, Napa, California, October 1993.

....as a code optimization and resource management framework. Examples of code, or fast path optimizations include Synthesis [60] Synthetix [85] PathIDs [56] Protocol Accelerators [107] and integrated layer processing [16, 1] Examples in the second category include processor capacity reserves [64], distributed migrating threads [19, 37] and Rialto activities [52] These related works do not attempt to define an explicit and universal path abstraction, but are a source of interesting examples of how paths can be employed. The work on Synthetix is also interesting in that it introduces the ....

C. W. Mercer, S. Savage, and H. Tokuda. Processor capacity reserves: An abstraction for managing processor usage. In Proceedings of the Fourth Workshop on Workstation Operating Systems (WWOS-IV), pages 129--134, Napa, CA, October 1993. IEEE.

....by Wulf s postmortem on HYDRA C.mmp[Wulf81] EROS unifies domains of authority and processes into a single object known as a domain (Figure 2) A domain is a cgroup (known as the domain root) which contains: ffl A schedule capability. The EROS scheduler implements processor capacity reserves [Mercer93]. Schedule capabilities convey the authority for a running domain to execute instructions under a particular scheduling reserve. 2 THE OBJECT ARCHITECTURE 4 ffl A keeper start capability naming the domain (the keeper) responsible for handling execution faults incurred by this domain. ffl A ....

Clifford W. Mercer, Stefan Savage, and Hideyuki Tokuda. "Processor Capacity Reserves: An Abstraction for Managing Processor Usage," Proceedings of the Fourth Workshop on Workstation Operating Systems (WWOS-IV), October 1993

....to the AQUA s transparent adaptation model. Applications specify the adaptation policy to a QoS server, which initiates degradation. Chen Lee et al. have investigated predictable communication protocol processing in a realtime Mach [9] The approach makes use of processor capacity reservation [11] to schedule realtime threads that perform I O in a Mach server. The approach uses a separate thread per I O stream. This work has also investigated policies to be placed in a user level dynamic QoS server [8] This concept is similar to the resource control servers in AQUA (for example, the RAP ....

C. W. Mercer, S. Savage, and H. Tokuda. Processor Capacity Reserves: An Abstraction for Managing Processor Usage. In Proceedings of the Fourth Workshop on Workstation Operating Systems (WWOS-IV), October 1993.

....previous reservations, and if so, returns a capability to an appropriate kernel reserve. This reserve capability can be placed in the schedule slot of a process s root node; all processes sharing a given reserve capability will run under the named reserve. In contrast to previous implementations [Kit93, Mer93], Processor reserves are not inherited across IPC operations. Priority inheritance raises a host of protection domain violation issues if reserves are inherited, a caller might call a service and then shut off its reserve, denying service to other callers. Reserve inheritance lends itself to ....

C. W. Mercer, S. Savage and H. Tokuda. "Processor Capacity Reserves: An Abstraction for Managing Processor Usage," in Proc. 4th Workshop on Workstation Operating Systems, October 1993.

....resulting system. For other resources, such as filesystem buffers, disk bandwidth, and lock access, the control if any is equally poor. Real time schedulers also lack modularity, and impose onerous restrictions on applications. However, a higherlevel processor capacity reserve abstraction [10] provides limited control of processor usage across protection boundaries, similar to a restricted form of ticket transfers. Fair share schedulers allocate resources to groups or users in proportion to the number of shares they have been assigned, providing time averaged fairness over long ....

C. W. Mercer, S. Savage, and H. Tokuda. Processor capacity reserves: An abstraction for managing processor usage. In Proceedings of the Fourth Workshop on Workstation Operating Systems, pages 129--134, Oct. 1993.

....code along the fast path, or ffl improving resource management. Examples of fast path optimizations include Synthesis [19] Synthetix [24] PathIDs [17] Protocol Accelerators [29] and integrated layer processing [4, 1] Examples in the second category include processor capacity reserves [21], distributed migrating threads [5, 9] and Rialto activities [16] Because space does not permit us to contrast all of this work in detail, we simply point out that the path abstraction as presented in this paper is an attempt at unifying these various ideas. In particular, the proposed ....

C. W. Mercer, S. Savage,and H. Tokuda. Processor capacity reserves: An abstraction for managing processor usage. In Proc. of the 4th Workshopon Workstation Operating Systems (WWOS-IV), pages 129--134, Oct. 1993.

....real time system when the task set is static, and as a soft real time system when the task set is dynamic. We now describe our processor reservation model. 3. Processor Capacity Reserves Processor capacity reserves provide an abstraction for allocating processor cycles in a real time system [8, 9]. It allows programs to request processor reservations which are expressed as a percentage of the processor and an associated period called the reservation period. For example, a program can request 30 of the processor every 100 ms which amounts to 30 ms of computation time every 100 ms. ....

....programs that would overrun their reservations and thereby prevent the overruns from taking over cycles from other activities. The design is presented in more detail in a technical report [9] and in another paper we present a brief description of the model and an implementation in Real Time Mach [8]. We are currently extending this enforcement philosophy of resource usage to other system resources as well. 4. Concluding Remarks In this paper, we have explored the similarities and differences between hard real time systems and multimedia systems. The similarities allow us to apply the ....

C. W. Mercer, S. Savage, and H. Tokuda. Processor Capacity Reserves: An Abstraction for Managing Processor Usage. In Proceedings of the Fourth Workshop on Workstation Operating Systems (WWOS-IV), October 1993.

No context found.

Clifford W. Mercer, Stefan Savage, Hideyuki Tokuda, Processor Capacity Reserves: An Abstraction for Managing Processor Usage, in Proceedings of the IEEE Fourth Workshop on Workstation Operating Systems (WWOS-IV), 14-15 Oct. 1993, IEEE Comp. Soc. Press, pages 129-134

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC