Jain, P., P. Kudva and G. Gopalakrishnan (1989). Towards a verification technique for large synchronous circuits. In: International Conference on Computer Design. Home/Search Document Details and Download
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Symbolic Simulation-Based Techniques For Debugging Discrete.. - Reich (Correct)
....used in analysis of traditional programming languages. Thus, it seems likely that the SPDS could be adapted to model the features of logic in other programming languages for PLCs or general purpose computers. Symbolic Simulation has also been used to model digital circuits (Bryant, 1989; Jain et al. 1989), so SSBD like methods can probably be applied. 8.3 Future Work This project was undertaken with the goal of producing a usable prototype tool and evaluating the SSBD technique for debugging. An important next step is further development of the theoretical framework and a formal proof of ....
Jain, P., P. Kudva and G. Gopalakrishnan (1989). Towards a verification technique for large synchronous circuits. In: International Conference on Computer Design.
A Methodology for Formal Hardware Verification, with Application.. - Beatty (1993) (11 citations) (Correct)
....that each signal is assigned a value exactly once, regardless of execution path. This corresponds to the absence of conflicting drivers or floating nodes in the design. Priam has been used within Bull to verify actual designs, and a VHDL based version has been marketed. Jain and Gopalakrishnan [142, 141] examined the use of parametric Boolean formulas in symbolic simulation. In their view of symbolic simulation, which they implement with Cosmos, circuit state is established, inputs are applied, and then outputs and state are checked. This will work for circuits which have no input constraints or ....
Prabhat Jain, Prabhakar Kudva, and Ganesh Gopalakrishnan. Towards a verification technique for large synchronous circuits. Computer-Aided Verification, 1992.
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