Black Jr., W.C., D.A. Hodges, "Time interleaved converter arrays", IEEE Journal of Solid-State Circuits, Dec. 1980, vol. SC-15, no.6, pp. 1022-9  Home/Search   Document Not in Database   Summary   Related Articles   Check

....sampling, equalization, estimation I. INTRODUCTION HERE is an ever increasing need for faster A D converters (ADCs) in modern communications technology, such as radio base stations or VDSL modems. To achieve high enough sample rates, an array of M ADCs, interleaved in time, can be used [1], 2] see Figure 1. The time interleaved ADC system works as follows: The input signal is connected to all the ADCs. delay, Ts sampling ADC 0 ADC 1 ADC 2 ADCM 1 y 1 y 2 y U X Fig. 1. A time interleaved ADC system. M parallel ADCs are used with the same master clock. The clock is ....

....parentheses. Sinusoidal input signal Angular frequency: # 0 [0.01, 3. 1] # 0 =1) Number of data per ADC: N [2 , 2 16 ] N =2 ) Number of ADCs: M [2, 16] M =4) Quantization noise, given as number of bits: n = 2, 16] n =10) Jitter variance: # [0, 1] (# jitter =0) Multisine input signal Maximum angular frequency: # 0 [0.01, 3.1] # 0 = 1) Number of tones: L [2, 256] L =64) Low pass filtered white noise [0.01, 3.1] Band pass filtered white noise, band width 10 of cut off frequency [0.01, 3.1] The true ....

W. Black and D. Hodges, "Time interleaved converter arrays," IEEE Journal of Solid-State Circuits, vol. SC-15, no. 6, pp. 1022--1029, December 1980.

....nonuniform sampling, equalization, I. INTRODUCTION HERE is an ever increasing need for faster A D converters (ADCs) in modern communications technology, such as radio base stations and VDSL modems. To achieve high enough sample rates, an array of M ADCs, interleaved in time, can be used [1], 2] see Figure 1. The time interleaved ADC system works as follows: The input signal is connected to all the ADCs. Each ADC works with a sampling interval of MT s , where M is the number of ADCs in the array and T s is the desired sampling interval. delay, Ts sampling ADC 0 ADC 1 ....

W. Black and D. Hodges, "Time interleaved converter arrays," IEEE Journal of Solid-State Circuits, vol. SC-15, no. 6, pp. 1022--1029, December 1980.

....calculate the Cramer Rao bound (CRB) for the time error estimates and compare it to simulations. We will also present some measurement results. But first we will describe the time interleaved ADC system and briefly review the time error estimation method presented in [1] Time interleaved ADCs [2], 3] can be used to increase the sample rate, see Figure 1. The time interleaved ADC system works as follows: The input signal is connected to all the ADCs. Each ADC works with a sampling interval of MT s , where M is the number of ADCs in the array and T s is the desired sampling ....

....estimation convergence Fig. 5. Convergence of time error parameter estimates for ADC system with four ADC (three parameters) The estimation error is here shown in fractions of Ts . Sinusoidal input signal Angular frequency: # 0 [0.01, 3. 1] # 0 =1) Number of data per ADC: N [2 , 2 16 ] (N =2 ) Number of ADCs: M [2, 16] M =4) Quantization noise, given as number of bits: n = 2, 16] n =10) Jitter variance: # [0, 1] # jitter =0) Multisine input signal Maximum angular frequency: # 0 [0.01, 3.1] # 0 = 1) Number of tones: L [2, 256] ....

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W. Black and D. Hodges, "Time interleaved converter arrays," IEEE Journal of Solid-State Circuits, vol. SC-15, no. 6, pp. 1022--1029, December 1980.

....speed classes, based on the number of FO4 delays per bit time. Most high speed transceivers run at about 4 FO4 delays per bit, and transmit data on both the rising and falling edges of an internal clock [1] 6] 15] Time interleaving allows bit rates faster than the internal clock rate [16][18], by using parallel transmitters and receivers which are clocked with phase shifted versions of the internal clock. An interleaving ratio of 8 is shown in Figure 2.2, and has been used to achieve bit times of approximately 1 FO4 [3] 10] 52] Time interleaving is needed to achieve such short bit ....

....Both the use of large transistors and series offset cancellation techniques limit the bandwidth of comparators. Increasing the sample rate through time interleaving exacerbates the problem by increasing input and output capacitance. Perhaps as a result, previous work in time interleaved ADCs [18][19] 20] has focused on area and power savings at much lower sample rates. The receiver presented in Chapter 3 increases 1. Sampling before averaging or interpolating would allow high bandwidth and may avoid offset calibration or reduce input capacitance, respectively. ....

W.C. Black Jr., D.A. Hodges, "Time interleaved converter arrays", IEEE Journal of Solid-State Circuits, Dec. 1980, vol. SC-15, no.6, pp. 1022-9

....the input signal passes to the output of each channel without being filtered. Because the signal sees only the center tap of the filter, the other filter coefficients may be chosen to optimally suppress the quantization noise. The time interleaved A D converter is similar to the A D converter [5]. Instead of a Hadamard sequence multiplying the input and output, an identity matrix is used. With the identity matrix, the signal magnitude is decreased by a factor of (where is the number of channels) over the Hadamard modulation because the signal passes through only one channel at any given ....

W. C. Black and D. A. Hodges, "Time-interleaved converter arrays," IEEE J. Solid-State Circuits, vol. SC-15, pp. 1022--1029, Dec. 1980.

....serious difficulties due to mismatches [14] Tones at f ck M and fixed pattern noise are generally caused by offset mismatches and sideband modulation around f ck M is introduced due to gain mismatches. The dynamic performance is severely affected by the timing mismatch among the channels [5][6] 15 Figure 2.9 Block diagram of an interleaved ADC. V in N bits Sub ADC 1 Digital Output CK 1 M x f ck SHA 1 N bits Sub ADC 2 CK 2 SHA 2 N bits Sub ADC M CK M SHA M CK M CK 2 CK 1 t T 1 (M 1)T 1 16 2.2.5 Interpolating Architecture As mentioned in Section 2.2.1, one of the ....

W. Black and D. A. Hodges, "Time Interleaved Converter Arrays," IEEE J. Solid-State Circuits, vol. SC-15, pp. 1022-1029, Dec 1980.

....passes to the output of each channel without being filtered. Because the signal sees only the center tap of the filter, the other filter coefficients may be chosen to optimally suppress the quantization noise. The time interleaved A D converter is similar to the Pi Delta Sigma A D converter [5]. Instead of a Hadamard sequence multiplying the input and output, an identity matrix is used. With the identity matrix, the signal magnitude is decreased by a factor of M (where M is the number of channels) over the Hadamard modulation because the signal passes through only one channel at any ....

W. C. Black and D. A. Hodges, "Time-Interleaved Converter Arrays," IEEE J. SolidState Circuits, vol. SC-15, no. 6, pp.1022-1029, Dec. 1980.

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Black Jr., W.C., D.A. Hodges, "Time interleaved converter arrays", IEEE Journal of Solid-State Circuits, Dec. 1980, vol. SC-15, no.6, pp. 1022-9

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W. Black and D. Hodges, "Time interleaved converter arrays," IEEE Journal of Solid-State Circuits, vol. SC-15, no. 6, pp. 1022--1029, December 1980.

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