Shyh-Jye Jou and I-Yao Chuang. Low-power globally asynchronous local synchronous design using self-timed circuit technology. In International Symposium on Circuits and Systems, volume 3, pages 1808--1811, June 1997.  Home/Search   Document Not in Database   Summary   Related Articles

....The synchronous register allows to save a data value at the next active clock edge. 3 Reduction of power consumption of hardware nodes Power dissipation of sequential circuits is proportional to the used clock frequency and is a design constraint for embedded systems. Numerous approaches like [4] and [1] present solutions to reduce power. Here, we propose a gated clock [1] see Fig. 3a) which allows to switch off parts of a sequential circuit that are actually not in use. Our implementation makes use of the handshake protocol between synchronous subsystems as proposed in Section 2.1. The ....

Shyh-Jye Jou and I-Yao Chuang. Low-power globally asynchronous local synchronous design using self-timed circuit technology. In International Symposium on Circuits and Systems, volume 3, pages 1808--1811, June 1997.

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