Min S. L. and Baer J. L. A Timestamp based Cache Coherence Scheme. In Proceedings of the 1989.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....point is the most simplistic software approach, but it produces the poorest cache performance. More sophisticated software schemes use the compiler to statically analyze data references and insert instructions in the user code to selectively invalidate cache blocks at certain program points [7, 8, 9, 10, 24]. Unfortunately, static analysis of data references may be hampered by obscure reference patterns, such as array indexing and pointers, for example, and by conditional branches and unknown side effects of procedure calls. Under such circumstances, the compiler must conservatively invalidate the ....

S. L. Min and J. L. Baer. A timestamp--based cache coherence scheme. International Conference on Parallel Processing, pages 23--32, 1989.

....location, seem more promising for large scale systems. However, directories can require large amounts of additional storage and directory maintenance operations may substantially increase network traffic. Others researchers suggest that caches include ver sion number based support for coherence[4, 12]. Drawbacks to these schemes include dedication of precious cache real estate to version numbers (decreasing the amount of useful data that the cache can hold) and the additional hardware complexity. A promising alternative to hardware based solutions for coherence is to use compilers to ....

S. Min and J. Baer. A timestamp-based cache coherence scheme. In Proc. of the 1989.

....cache coherence schemes also use prevention techniques. Stale reference avoidance is a more relaxed coherence model than the prevention technique. It allows the existence of stale data while avoiding stale references to them at run time. Examples of this approach include the Timestamp based scheme [11] and the Version Control scheme [3] Similar to deadlock recovery, we can also employ stale reference recovery technique. This technique allows the stale reference to occur but it performs actions to recover to the previous state when the stale reference is detected. This approach has not been ....

....and software support are provided to invalidate the entire cache or a single cache line explicitly or implicitly, and thus cache coherence can be enforced under the programmer s control. 3. 2 Hardware supported compiler directed coherence schemes Several compiler directed cache coherence schemes [2, 3, 4, 6, 9, 11] that require some hardware support have been proposed recently. These schems can achieve better performance, but require 7 Scheme Coherence Intertask Storage Runtime Technique locality Overhead overhead SI prevention none O(1) invalidate FSI detection, read only O(1) invalidate prevention ....

[Article contains additional citation context not shown here]

S. L. Min and J.-L. Baer. A Timestamp-based Cache Coherence Scheme. Proceedings of the 1989 International Conference on Parallel Processing, I:23--32, 1989.

....its operations. 2 Delta cache protocols are hardware, directory protocols. Hardware protocols manage caches dynamically without direction from the programmer. They require run time communication to maintain memory coherence, but, for this reason, are less conservative than software protocols [ChV88, MiB89], protocols that depend on the programmer or compiler to manage caches with little or no hardware support. In choosing to focus on hardware protocols, we do not dismiss the benefits of using static information in reducing the cost of cache coherence. Several software hardware hybrid protocols that ....

S. L. Min and J. Baer, A Timestamp-based Cache Coherence Scheme, Int. Conf. on Parallel Processing 1(1989), 23-32.

....in invalidation based schemes. Considerably more experience is needed in analyzing applications to determine how much informationcan be easily gleaned to automate the process of using these primitives in the compiler. The work by Cytron et al. [8] Cheong and Veidenbaum [6, 5] and Min and Baer [26] have goals similar to ours in attempting to reduce the global communication by providing software directed cache coherence. 6 Performance Evaluation In this section, we compare the performance of the above mentioned memory systems using a set of applications. We simulate the relevant details of ....

S. L. Min and J-L. Baer. A Timestamp-based Cache Coherence Scheme. In Proceedings of the 1989 International Conference on Parallel Processing, pages I: 23--32, August 1989.

....memory based program, than to a message passing based program. For these reasons and others, much research has been done on how to define and implement distributed shared memory, both from the theoretical point of view [2, 3, 6, 10, 11, 13, 22, 26, 27, 28] and from the practical point of view [14, 17, 18, 19, 21, 31, 32, 33]. However, most of this work ignores the possibility of failures and does not allow processors to join an ongoing computation, in order to speed it up. On the other hand, it is clear that if distributed shared memory is to be implemented in massively parallel computers, or over a network of ....

S. Min and J. Baer. A Timestamp-Based Cache Coherence Scheme. In Proc. International Conf. on Parallel Processing, pages I--23--32, 1989.

....in invalidation based schemes. Considerably more experience is needed in analyzing applications to determine how much information can be easily gleaned to automate the process of using these primitives in the compiler. The work by Cytron et al. [10] Cheong and Veidenbaum [7, 6] and Min and Baer [29] have goals similar to ours in attempting to reduce the global communication by providing software directed cache coherence. 6 Performance Evaluation In this section, we compare the performance of the above mentioned memory systems using a set of applications. We simulate the relevant details ....

S. L. Min and J-L. Baer. A Timestamp-based Cache Coherence Scheme. In Proceedings of the 1989 International Conference on Parallel Processing, pages I: 23--32, August 1989.

....accesses and thereby reduce both average memory latency and network traffic. However, maintaining cache coherence for such systems is still a challenge. Hardware directories can be very effective, but are too expensive for largescale multiprocessors. As an alternative, compiler directed techniques [12, 14, 15, 16, 21, 27, 38, 39, 49] can be used to maintain coherence. In this approach, cache coherence is maintained locally without directory hardware, thus avoiding the complexity and overhead associated with hardware directories. Most schemes require compile time analysis to detect possible stale data accesses and to ....

....segment unit, are supported. The Cedar uses a shared cache to avoid coherence problems within each cluster. Data coherence is maintained among clusters by moving data explicitly between cluster and global memories using data movement instructions. Several compiler directed cache coherence schemes [12, 14, 15, 16, 21, 27, 38, 39] have been proposed recently. These schemes give better performance, but demand more hardware and compiler support than the previous schemes. They require a more precise program analysis to maintain coherence on a reference basis [12, 13, 21] as opposed to the program region basis used by previous ....

[Article contains additional citation context not shown here]

S. L. Min and J.-L. Baer. A Timestamp-based Cache Coherence Scheme. Proceedings of the 1989 International Conference on Parallel Processing, I:23--32, 1989.

....that location, seem more promising for large scale systems. However, directories can require large amounts of additional storage and directory maintenance operations may substantially increase network traffic. Others researchers suggest that caches include version number based support for coherence[4, 12]. Drawbacks to these schemes include dedication of precious cache realestate to version numbers (decreasing the amount of useful data that the cache can hold) and the additional hardware complexity. A promising alternative to hardware based solutions for coherence is to use compilers to analyze ....

S. Min and J. Baer. A timestamp-based cache coherence scheme. In Proc. of the 1989 International Conference on Parallel Processing, volume 1, pages 23--32, Aug. 1989.

....for these data. Furthermore, data movement instructions are provided so that the programmer can explicitly move data between the cluster and global memories. By using these software mechanisms, coherence can be maintained for globally shared data. Several compiler directed cache coherence schemes [10, 12, 13, 14, 18, 21, 29, 30] have been recently proposed. These schemes give better performance, but demand more hardware and compiler support than the previous schemes. They require a more precise program analysis to maintain coherence on a reference basis [10, 11, 18] instead of a program region basis compared to the ....

....called the two phase invalidation (TPI) scheme which relies mostly on compiler analysis, yet al..so provides a reasonable amount of hardware support. This approach has a long history of predecessors, including C. mmp [38] IBM s RP3 [6] Illinois Cedar [27] and several recently proposed schemes [10, 14, 12, 13, 18, 21, 29, 30]. The TPI scheme can be implemented on a large scale multiprocessor using off the shelf microprocessors, and can be adapted to various cache organizations, including multi word cache lines and byte addressable architectures. Several system related issues, including coherence enforcement for ....

S. L. Min and J.-L. Baer. A Timestamp-based Cache Coherence Scheme. Proceedings of the 1989 International Conference on Parallel Processing, I:23--32, 1989.

....atomic actions. 6.1. RELATED WORK Delta cache protocols are hardware, directory protocols. Hardware protocols manage caches dynamically without direction from the programmer. They require run time communication to maintain memory coherence, but are less conservative than software protocols, e.g. [ChV88, MiB89], protocols that use static analysis by the programmer or compiler to manage caches with little or no hardware support. In choosing to focus on hardware protocols, we do not dismiss the benefits of using static information in reducing the cost of cache coherence. Several software hardware hybrid ....

S. L. Min and J. Baer, A Timestamp-based Cache Coherence Scheme, Int. Conf. on Parallel Processing 1(1989), 23-32.

....read is sufficient to create a potential stale reference. We call this sequence of events a stale reference sequence. 1. 3 Coherence mechanism and hardware support In our cache coherence scheme, each epoch is assigned a unique epoch number which is similar to the version number in previous schemes [3, 6, 7, 14]. The epoch number is stored in an n bit register in each processor, called epoch counter (R counter ) and is incremented at the end of every epoch by each processor individually. Every word in a cache is associated with an n bit timetag that records the epoch number when the cache copy is ....

....graph. 4 Conclusion We propose improved compiler algorithms for detecting stale data references in the presence of procedures calls. Procedure calls can introduce side effects at a call site and hidden context at the beginning of a procedure, which can limit compiler directed coherence schemes [2, 4, 3, 10, 13, 14] to exploit locality only within procedure boundaries. Previous algorithms use cache invalidation [5, 8] or selective inlining [8] to solve the problem. However, invalidation at procedure boundaries incur significant performance penalty especially if a program contains many small procedures in its ....

S. L. Min and J.-L. Baer. A Timestamp-based Cache Coherence Scheme. 1989 International Conference on Parallel Processing, I:23--32, 1989.

....an extended tag field per cache word, one modified memory access instruction, and a counter called the epoch counter in each processor. By using the epoch counter as a system wide version number, the scheme simplifies the cache hardware of previous version control [5] or timestamp based schemes [12], but still exploits most of the temporal and spatial locality across task boundaries. We present a compiler algorithm to generate the appropriate memory access instructions for the proposed scheme. The algorithm is based on a data flow analysis technique. It identifies potential stale references ....

....average memory latency and the network traffic. Having multiple cached copies of a shared memory location, however, can lead to erroneous program behavior unless coherence is maintained. Existing solutions for large scale multiprocessors include hardware directories [1, 10] and software techniques [2, 3, 5, 6, 11, 12, 14, 15]. By maintaining sharing information at runtime, directory based schemes can identify stale data accurately, preserving more 1 This work is support in part by the National Science Foundation under Grant No. MIP 89 20891, MIP 93 07910. ISSN 1063 9535. Copyright (c) 1994 IEEE. All rights ....

[Article contains additional citation context not shown here]

S. L. Min and J.-L. Baer. A Timestamp-based Cache Coherence Scheme. 1989 International Conference on Parallel Processing, I:23--32, 1989.

....[2, 21, 22] Although these hardware schemes can precisely identify stale data by maintaining sharing information at runtime, they substantially increase the hardware cost for the directory storage and require complex directory and cache controllers. As an alternative, compiler directed techniques [7, 9, 10, 15, 11, 17, 23, 24, 31] can be used to maintain coherence. In this approach, cache coherence is maintained locally without directory hardware, thus avoiding the complexity and overhead associated with hardware directories. They usually require compile time analysis to detect possible stale data accesses and to ....

S. L. Min and J.-L. Baer. A Timestamp-based Cache Coherence Scheme. Proceedings of the 1989 International Conference on Parallel Processing, I:23--32, 1989.

....a segment unit, are supported. The Cedar uses a shared cache to avoid coherence problems within each cluster. Data coherence is maintained among clusters using software. Each variable has a memory access attribute of either private or global . Several compiler directed cache coherence schemes [11, 13, 14, 21, 17, 27, 28] have been recently proposed. These schemes give better performance, but demand more hardware and compiler supports than the the previous schemes. They require a more precise program analysis to maintain coherence on a reference basis [11, 12, 21] instead of a program region basis compared to the ....

....called the two phase invalidation (TPI) scheme which relies mostly on compiler analysis, but which also needs a reasonable amount of hardware support. This approach has a long history of predecessors, including C. mmp [36] IBM s RP3 [6] Illinois Cedar [25] and several recently proposed schemes [11, 13, 14, 21, 17, 27, 28]. The TPI scheme can be implemented on a large scale multiprocessor using off the shelf microprocessors, and can be adapted to various cache organizations, including multi word cache lines and byte addressable architectures. Several system related issues, including coherence enforcement for ....

S. L. Min and J.-L. Baer. A Timestamp-based Cache Coherence Scheme. Proceedings of the 1989 International Conference on Parallel Processing, I:23--32, 1989.

....of our proposed scheme. In Section 2, we give the notation used throughout the paper. Section 3 reviews previous software assisted approaches to enforcing cache coherence. In Section 4, a complete description of our approach is given. A correctness proof of our proposed scheme is given elsewhere [29] and is omitted here. Section 5 gives a quantitative comparison of our scheme with previous approaches. Section 6 provides some concluding remarks. 2 Definitions Programs written for shared memory multiprocessors may use explicit parallel constructs or may be conventional sequential programs ....

....be re used either in future epochs or in the current epoch instance. From the above considerations, each write operation to a shared variable in a parallel program belongs to zero, one or both of the following two overlapping classes (cf. Figure 6; for a more formal definition of the markings, see [29]) 1. T W (timestamped writes) 2. PW (provisional writes) A write operation in an epoch belongs to the first class (i.e. is marked as timestamped write, T W) if the memory location written by it cannot be overwritten by writes from different instances of the same epoch. As we will see later, the ....

S. L. Min and J.-L. Baer. A timestamp-based cache coherence scheme. In Proceedings of the 1989 International Conference on Parallel Processing, Vol. I Architecture, pages 23--32, August 1989.

.... coherence mechanism to prevent any processor from using a stale memory value [19] Current solutions to the cache coherence problem for large scale multiprocessor systems interconnected with multistage networks can be classified into two main types, specifically, software controlled mechanisms [6, 7, 8, 9, 22] and hardware directory mechanisms [1, 3, 4, 16, 29] Softwarecontrolled mechanisms use compile time analysis to insert extra instructions into the program that force each processor to invalidate stale entries in their caches before they are referenced. Due to the limitations of compile time ....

....the coherence enforcement. If the compiler is unable to determine the precise characteristics of a particular memory reference, it conservatively marks the reference and then relies on the directory to perform the necessary coherence operations. Conversely, software controlled coherence mechanisms [6, 7, 8, 9, 22] rely on the compiler to ensure the correctness of coherence enforcement while using hardware assistance to store dynamically changing information. For instance, the S D coherence mechanism [7] uses compile time analysis to partition a program into phases called epochs. A directory at the shared ....

S. L. Min and J. L. Baer. A timestamp--based cache coherence scheme. International Conference on Parallel Processing, pages 23--32, 1989.

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Min S. L. and Baer J. L. A Timestamp based Cache Coherence Scheme. In Proceedings of the 1989.

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