J. Teich, L. Thiele, and L. Zhang, "Partitioning Processor Arrays under Resource Constraints," Journal of VLSI Signal Processing, vol. 17, no. 1, pp. 5--20, Sept. 1997. Home/Search Document Details and Download
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Synthesis of FPGA Implementations from Loop Algorithms - Bednara, Teich (2001) Self-citation (Teich) (Correct)
.... for converting imperative loop programs to single assignment code (this front end is similar to the approach in [3] The parallelized algorithm is now subject to several equivalence preserving transformations such as localization of data dependences, affine index transformations, partitioning [11, 12, 13], and automatic control generation [10] For the generation of synthesizable HDL code (performed by the PARO back end) we assume that the algorithm is already partitioned and localized. 3 Requirements for Hardware Mapping In this section, we define a piecewise regular algorithm and develop ....
J. Teich, L. Thiele, and L. Zhang. Partitioning processor arrays under resource constraints. Int. Journal of VLSI Signal Processing, 17(1):5--20, September 1997.
Compile-Time Optimization of Dynamic Hardware Reconfigurations - Teich, Fekete, Schepers (1999) (3 citations) Self-citation (Teich) (Correct)
....interest using a new branch andbound technique. Other variants and extensions (like FeasA FindS and MinA FindS) require additional mathematical machinery and will be dealt with in future work. The proposed methodology might be particularly useful for prototyping piecewise regular algorithms [11, 12, 13] in hardware. In this sense, the task graph might be seen as a system level view of the dependencies of communicating regular subalgorithms, each being presynthesized and stored in an FPGA module library, and represented by a relocatable rectangle of cells and its execution time. 2 ....
J. Teich, L. Thiele, and L. Zhang. Partitioning processor arrays under resource constraints. Int. Journal on VLSI and Signal Processing Systems, 17(1):5--20, 1997.
The Journal of VLSI Signal Processing---Systems for Signal, .. - Fl Systolic Design (Correct)
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J. Teich, L. Thiele, and L. Zhang, "Partitioning Processor Arrays under Resource Constraints," Journal of VLSI Signal Processing, vol. 17, no. 1, pp. 5--20, Sept. 1997.
True Motion Estimation - Theory, Application, and Implementation - Chen (1998) (Correct)
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J. Teich, L. Thiele, and L. Zhang, "Partitioning Processor Arrays under Resource Constraints," Journal of VLSI Signal Processing, vol. 17, no. 1, pp. 5--20, 1997.
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