V. Gyuris and A.P. Sistla. On-the- y model checking under fairness that exploits symmetry. Formal Methods in System Design, 15(3):217-238, November 1999.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... summarised in [20] The complexity of the orbit problem and examples of groups where the orbit problem is easy to solve are considered in [13] These early results are extended to incorporate the notions of fairness [22] and partial order reduction [25] and an on the y extension is introduced [36]. Symmetries in logical subformulas are exploited [2, 50] in LTL and CTL respectively. Symmetry reductions have been implemented within existing model checkers. For example the SMV system [51] includes a symmetry reduction package which uses the scalarset approach of Ip and Dill [45] A ....

V. Gyuris and A.P. Sistla. On-the- y model checking under fairness that exploits symmetry. Formal Methods in System Design, 15(3):217-238, November 1999.

....We illustrate the method on a non trivial example of a cache protocol, provided by Steve German. 1 Introduction Automatic veri cation of in nite state systems in general, and parameterized systems in particular, have been the focus of much research recently (see, e.g. ES96,ES97,CFJ96,GS97,ID96,LS97,RKR 00] Most of this research concentrates on model checking techniques for veri cation of such systems, using symmetry reduction and similar methods to make model checking more tractable. In this paper we present a method for the automatic veri cation of a certain class of ....

....gurations of processes as a word in a regular language. Unfortunately, many of the systems analyzed by this method cause the analysis procedure to diverge and special acceleration procedures have to be applied which, again, requires user ingenuity and intervention. The works in [ES96,ES97,CFJ96,GS97] study symmetry reduction in order to deal with state explosion. The work in [ID96] detects symmetries by inspection of the system description. Perhaps the closest in spirit to our work is the work of McMillan on compositional model checking (e.g. McM98] which combines automatic abstraction ....

V. Gyuris and A. P. Sistla. On-the- y model checking under fairness that exploits symmetry. In In , O. Grumberg, editor, Proc. 9 th Intl. Conference on Computer Aided Verication, (CAV'97), volume 1254 of Lect. Notes in Comp. Sci. , Springer-Verlag, 1997.

....gurations of processes as a word in a regular language. Unfortunately, many of the systems analyzed by this method cause the analysis procedure to diverge and special acceleration procedures have to be applied which, again, requires user ingenuity and intervention. The works in [ES96,ES97,CEFJ96,GS97] study symmetry reduction in order to deal with state explosion. The work in [ID96] detects symmetries by inspection of the system description. Closer in spirit to our work is the work of McMillan on compositional model checking (e.g. McM98b] which combines automatic abstraction with ....

V. Gyuris and A. P. Sistla. On-the- y model checking under fairness that exploits symmetry. In CAV'97, LNCS 1254, 1997.

....here only a few papers that are most closely related to our work, which is in the context of asynchronous systems. For a more complete overview we refer to the bibliography of [19] Emerson and Sistla have applied the idea to CTL model checking in [10] with extensions to fairness in [13] and [15]. In [11] Emerson and Tre er extended the concepts to real time logics, while in [12] they considered systems that are almost symmetric. Clarke, Enders, Filkorn, and Jha used symmetries in the context of symbolic model checking in [4] Emerson, Jha, and Peled, and more recently Godefroid, have ....

V. Gyuris, A.P. Sistla, On-the y model checking under fairness that exploits symmetry, in O. Grumberg (ed.), Proc. of CAV'97 (Computer Aided Verication), LNCS 1254, 232-243, Springer, 1997.

....here only a few papers that are most closely related to our work, which is in the context of asynchronous systems. For a more complete overview we refer to the bibliography of [19] Emerson and Sistla have applied the idea to CTL model checking in [10] with extensions to fairness in [13] and [15]. In [10] they outlined a method for ecient calculation of a canonical representative for a special case when the global state vector consists only of individual process locations (program counters) i.e. no variables are allowed. In [11] Emerson and Tre er extended the concepts to real time ....

V. Gyuris, A.P. Sistla, On-the- y model checking under fairness that exploits symmetry, in O. Grumberg (ed.), Proc. of CAV'97 (Computer Aided Verication), LNCS 1254, pp. 232-243, Springer, 1997.

....or . Various properties, such as deadlock freedom, of the net N can be checked by using a quotient reachability graph of N . For more on these properties and temporal logic model checking under symmetries, see e.g. Starke 1991; Jensen 1995; 1996; Clarke et al. 1996; Emerson and Sistla 1996; Gyuris and Sistla 1999]. The integration problem in the (inductive) generation of quotient reachability graphs is [Schmidt 1999; 2000b] Problem 3.2 Given a set Q of already visited markings and a newly generated marking M , nd out whether there is a marking M 0 2 Q such that M M 0 . There are three ....

....For many markings it may be the case that some automorphisms map the marking to itself. We now demonstrate how such marking stabilizers can be exploited and study what is the complexity of calculating them (cf. selfsymmetries of Jensen [1995; 1996] and state symmetry in [Emerson and Sistla 1996; Gyuris and Sistla 1999]) De nition 5.1 The stabilizer of a marking M is Stab(M) f 2 Aut(N) j (M) Mg : Clearly Stab(M) is a sub group of Aut(N) The algorithm of Schmidt [2000a] can be used to compute marking stabilizers. One way to exploit marking stabilizers is based on the following observation: Lemma 5.2 ....

GYURIS, V. AND SISTLA, A. P. 1999. On-the-y model checking under fairness that exploits symmetry. Formal Methods in System Design 15, 3 (Nov.), 217238.

.... both in the time and memory requirements (see e.g. 5, 17, 18, 25] The properties that one is able to check from reduced reachability graphs range from simple deadlock absence, safety and Petri net speci c properties [3, 4, 15, 17, 18] to full edged model checking of temporal logic formulae [1, 6, 7, 8, 12]. As the generation of the full reachability graph is to be avoided, we must nd the information generating the symmetries on the system description level. This information typically is a permutation group (under an arbitrary binary operator ) operating on some elements of the system ....

V. Gyuris and A. P. Sistla. On-the- y model checking under fairness that exploits symmetry. In Grumberg [11], pages 232-243.

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V. Gyuris, A.P. Sistla, On-the #y model checking under fairness that exploits symmetry, in O. Grumberg #ed.#, Proc. of CAV'97 #Computer AidedVeri#cation#, LNCS 1254, 232#243, Springer, 1997.

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