F. J. Kurdahi and A. C. Parker, "REAL: A program for register allocation, " oc. 24th Design Automation Conf., Miami Beach, FL, 1987, pp. 210--215.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....along the critical path [ Delta Delta Delta ; S 3 ; S 4 ; Delta Delta Delta ] the specification variable A is mapped to the register R 1 and along the critical path [ Delta Delta Delta ; S 7 ; S 8 ; Delta Delta Delta] it is mapped to R 3 . Many high level synthesis systems such as REAL [28], EMUCS [47] and EASY [45] use value based register optimization approach. In this approach, the register optimization problem can be modeled as a channel routing problem; the life span of each value is modeled as a net interval. The minimum number of tracks corresponds to the number of registers ....

Kurdahi, F. and A. Parker: 1987, `REAL: A Program for REgister ALlocation'. 24th Design Automation Conference.

....phase groups carriers such that no two carriers in the same group are simultaneously active. Each group of carriers is then assigned to a register module whose bit width is the maximum of the bit widths of all carriers in the group. Various register optimization strategies have been proposed [20]. Our register optimization algorithm is based on a clique partitioning heuristic on the lines proposed by Tseng and Siewiorek [21] Interconnect Optimization The goal of interconnect optimization is to assign an interconnect path to each value transfer in the dfg. Interconnect paths are formed ....

F. Kurdahi and A. Parker, "REAL : A Program for REgister ALlocation," 24th Design Automation Conference, pp. 210-215, 1987.

....of obtaining the minimum number of reconfiguration contexts using a LeftEdge based algorithm. The Left Edge algorithm is well known for its application in channel routing tools for physical design automation. It has been also adapted to solve the register allocation problem in high level synthesis [15]. We have adapted and used this algorithm to address our problem. Using this approach we always get optimal results for the number of reconfiguration contexts. See [20] for details on this algorithm. 5. Experiments and Results In this section, we explain a case study of our codesign methodology ....

F. J. Kurdahi, A. C. Parker, "REAL: A Program for Register Allocation", Proc. 24 Design Automation Conference, DAC'87.

....and if arrays are treated, they are flattened and each array element is considered a separate scalar. Through the use of scheduling techniques like the left edge algorithm the lifetime of each scalar is found so that scalars with non overlapping lifetimes can be mapped to the same storage unit [6]. Techniques such as clique partitioning are also exploited to group variables that can be mapped together [7] A good introduction to the scalar based storage unit estimation can be found in [4] Common to all of them is that they break down when used for large multi dimensional arrays, due to ....

Kurdahi F. J., and Parker, A. C., "REAL: A Program for REgister ALlocation", Proc. 24th DAC, 1987, pp. 210-5

....algorithms (datapath is built from scratch) Greedy constructive approaches [7] linear programming approaches [8, 9] and branch and bound [5, 10] belong to the first group. The second group covers all the graph theoretical formulations such as clique partitioning [3] left edge algorithm [11], and weighted bipartite matching algorithm [12] Iterative improvement algorithms can achieve high quality solutions at the expense of using CPU intensive techniques, such as hillclimbing [13] or simulated evolution [14] From all the existing techniques, only greedy constructive methods and ....

F.J. Kurdahi and A.C. Parker. REAL: A Program for Register Allocation. In Proc. of the 24th ACM/IEEE Design Automation Conference, pages 210-215, 1987.

....the binding solutions and when it does, it causes little change in P total . This is also seen in Tables 2 and 3, where total P total is only 1.072 on average. The number of registers (obtained by performing register allocation on a functionally pipelined data path by a program such as REAL [KuAl87]) will also not change as the life time of data values in the data flow graph will not change after the permutation (see Section 4.3) The circuit speed will not change as we only permute compatible operations in the same c step (same column in the EAT) and the number of c steps is not altered. ....

Fadi Kurdahi, Alice Parker, "REAL: A Program for Register Allocation", In Proceeding of 24th Design Automation Conference, June 1987.

....and if arrays are treated, they are flattened and each array element is considered a separate scalar. Through the use of scheduling techniques like the left edge algorithm the lifetime of each scalar is found so that scalars with non overlapping lifetimes can be mapped to the same storage unit [11]. Techniques such as clique partitioning are also exploited to group scalars that can be mapped together [14] A good introduction to scalar based storage unit estimation can be found in [7] Common to all of them is that they break down when used for large multi dimensional arrays, due to the ....

F.J. Kurdahi and A.C. Parker, "REAL: A Program for REgister ALlocation ", Proc. 24th DAC, June-July 1987, pp. 210-5

.... much more time to be scheduled than originally as shown in Figure 1(c) The scheduling of the debug I O operations variables, and their assignment to available pins, is performed using an interval graph representation of the (ASAP, ALAP) times of the I O operations, and the left edge algorithm [Kur87], ASAP ALAP , DO( max max prod X 1 ( max req X 1 ( 1min req X ( 1) ASAP ALAP , DO( max prod Y ( 1min prod Y 1 ( 1 , originally proposed for register module assignment. Figure 2(b) shows the (ASAP, ALAP) information for the debug I O operations in ....

....of 1 may be sufficient to satisfy them. In other words, the minimum debug periodicity required to satisfy the given 8 debug reads writes is 1. Consequently, let us try to schedule assign the added debug input output operations with a debug periodicity of 1. Application of the left edge algorithm [Kur87] on the corresponding interval graph is shown in Figure 3(b) As can be seen from Figure 3(b) only two of the four desired debug writes can be satisfied. Analysis of the interval graph shows that even though the ncc iop I O ( input pin is available in two control steps, 2 and 3 in ....

F.J. Kurdahi, A.C. Parker, "REAL: A Program for Register Allocation", DAC-87, pp. 210-215, 1987.

....A more detailed description of applying the pre packing on a real life design is discussed in the section 7.2. 4.2. Related work Almost all published techniques for dealing with the allocation of storage units have been scalar oriented and they employ a scheduling directed view (see e.g. KuPa87] BMB88] GRV90] SSP92] where the control steps of production consumption for each individual signal are determined beforehand. This applies also for memory register estimation techniques (see e.g. KuPa87] GDW93] DePa96] and their references) This strategy is mainly due to the fact ....

....units have been scalar oriented and they employ a scheduling directed view (see e.g. KuPa87] BMB88] GRV90] SSP92] where the control steps of production consumption for each individual signal are determined beforehand. This applies also for memory register estimation techniques (see e.g. KuPa87] GDW93] DePa96] and their references) This strategy is mainly due to the fact that applications targeted in conventional high level synthesis contain a relatively small number of signals (at most of the order of magnitude 10 3 ) The control data flow graphs addressed are mainly composed ....

F. J. Kurdahi, A. C. Parker, "REAL: a program for register allocation", Proc. of 24th ACM/IEEE Design Automation Conf., Miami FL, pp.210-215, June 1987.

....synthesis for manufacturing testing has been extensively discussed [29, 11, 20] Register sharing is explored when register allocation is performed. Many well known register allocation algorithms focus on either unconditional register sharing [39, 31, 12] or conditional register sharing [3, 17] for control data flow graphs that contain no loops. For control data flow graphs with loops, Stok and van den Born [37] proposed a method to break the loops at loop boundaries such that variables whose lifetimes cross a loop boundary are split and treated as two separate variables. When the two ....

F.J. Kurdahi and A.C. Parker, REAL: a program for REgister ALlocation, Design Automation Conference (1987) pp. 210--215.

....Finally, the results are presented of applying the approach to ATM cell processing applications. 2. Related work Until recently, almost all published techniques for dealing with the allocation of storage units have been scalaroriented and they employ a scheduling directed view (see e.g. [8, 1, 7, 12]) where the control steps of production consumption for each individual signal are determined beforehand. This applies also for memory register estimation techniques (see e.g. 8, 6, 5] and their references) This strategy is mainly due to the fact that applications targeted in conventional ....

....allocation of storage units have been scalaroriented and they employ a scheduling directed view (see e.g. 8, 1, 7, 12] where the control steps of production consumption for each individual signal are determined beforehand. This applies also for memory register estimation techniques (see e.g. [8, 6, 5] and their references) This strategy is mainly due to the fact that applications targeted in conventional high level synthesis contain a relatively small number of signals (at most of the order of magnitude 10 3 ) The control data flow graphs addressed are mainly composed of potentially ....

F. J. Kurdahi, A. C. Parker, "REAL: a program for register allocation", Proc. 24th ACM/IEEE Design Automation Conf., pp.210-215, June 1987.

....Floorplanning Figure 5 shows the specialization of our general datapath allocation algorithm for this problem environment. During the initial allocation, functional unit binding is performed by a Clique partitioning algorithm [27] and register binding is performed by a Left edge algorithm [28]. As a result, the minimal numbers of functional units and registers required are obtained. Next, floorplanning is performed to determine the one dimensional relative coordinates of each functional unit and register. Minimization of the number of maximum cuts is used as an object function for this ....

Kurdahi, F. J. and Parker, A. C., "REAL: A Program for REgister ALlocation," Proc. 24th DAC, pp.210-215, 1987.

....signals required to perform operations within an ALU at that iteration. To find this number, we use an expanded version of the activity selection algorithm y . This is a greedy algorithm capable y This algorithm is an extended version of the left edge algorithm used by many researchers such as [19]. of finding the best solution for one register in Theta(m) where m is the number of signals some of which are selected to be saved in that REG. Briefly, the signal with the smallest death time is selected and if it is compatible (no time conflict) with other signals in the register it will be ....

F. J. Kurdahi and A. C. Parker, "REAL: A Program for REgister ALlocation," Proc. 24rd Design Automat. Conf., July 1987.

....phase groups carriers such that no two carriers in the same group are simultaneously active. Each group of carriers is then assigned to a register module whose bit width is the maximum of the bit widths of all carriers in the group. Various register optimization strategies have been proposed [18]. Our register optimization algorithm is based on a clique partitioning heuristic on the lines proposed by Tseng and Siewiorek [19] Figure 3.6 shows the dfg following register optimization and binding. Interconnect Optimization The goal of interconnect optimization is to assign an interconnect ....

F. Kurdahi and A. Parker, "REAL : A Program for REgister ALlocation," 24th Design Automation Conference, pp. 210-215, 1987.

....difficult to estimate the switch requirement before scheduling has been performed. After scheduling, the hardware operator requirement and the storage requirement can be estimated more accurately. For straight line code the minimum storage cost can be easily obtained using the left edge algorithm [6]. At this stage a better estimate of the switch requirement can also be obtained for a point to point interconnection scheme. For a bus based interconnection scheme a reasonable estimate of switch requirement can be obtained after transfers have been mapped to buses [7] Thus, while working with ....

F. J. Kurdahi and A. C. Parker, "Real: A program for register allocation," Proceedings of the 24th Design Automation Conference, 1987.

....memories we have proved that the port assignment problem and its absolute and relative approximations are all NP hard. In section 5 we review the register optimization problem and introduce the register optimization problem for straight line code, which is known to be solvable in polynomial time [4]. In section 6 we generalize this problem to the register interconnect optimization problem for straight line code (SRIO) This problem is naturally encountered for simple instances for DPS problems. Through this problem we prove that the interconnect optimization as well as its constant bounded ....

....We shall use the results derived here in the subsequent sections of this paper. We now go over to register optimization and register interconnect optimization problems. 5 Register Optimization The aim of register optimization (RO) is to minimize the number of registers needed in the design [4]. Registers need to be used to store values between control steps. In the context of data path synthesis registers are needed to implement the variables used to describe the behaviour of the target system. In addition to the variables declared by the designer, some variables may be used at the ....

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F. J. Kurdahi and A. C. Parker, "Real: A program for register allocation," Proceedings of the 24th Design Automation Conference, 1987.

....registers. Compatibility graphs can be used to represent life cycles that do not overlap; clique partitioning of the compatibility graph yields a set of registers. Both coloring and clique partitioning are NP complete. However, efficient heuristics have been discovered for solving both problems. [3, 4, 5, 6] Register optimization techniques can be broadly classified into two categories: value based and carrier based. In the value based approach, register optimization is modeled as the problem of mapping data values produced and used by operations in a data flow graph representation of the ....

....value based approaches lend themselves to efficient algorithms, modeling value propagation across loop boundaries is difficult. Thus data dependent loops, especially those that cannot be unfolded, are not supported in most systems that employ value based approaches for register optimization. REAL [4], EMUCS [8] and EASY [9] use valuebased register optimization techniques. In the carrier based approach, register optimization is viewed as the problem of mapping carriers onto registers. Lifetime analysis of carriers is performed to establish compatibility relation between pairs of carriers. The ....

F. Kurdahi and A. Parker, "REAL : A Program for REgister ALlocation," 24th Design Automation Conference, pp. 210-215, 1987.

....should include a decision on: the number and type of memory units, the signal to memory binding for M D signals, and the detailed internal organization of the memory units. Note that this is fully complementary to the traditional high level synthesis step known as register allocation assignment [26, 13, 10, 16, 24] which deals with individual storage locations for scalars. A major drawback of such an approach is that the loop structure has to be destroyed by unrolling. This is unfeasible in video and image processing applications, and the like. Little work has been performed in the HLMM domain within a ....

....far are substantiated in Section 6, followed by conclusions and our future directions of research in Section 7. 2 Background memory allocation and M D signal assignment To our knowledge, almost all techniques tackling the storage allocation problem employ a scheduling driven scalar oriented view [26, 13, 2, 10, 1, 22, 24] where the control steps of production and consumption are assumed to be known for each individual scalar signal. This strategy is mainly due to the fact that applications targeted in conventional highlevel synthesis contain a relatively small number of signals (at most of the order of 10 3 of ....

F.J.Kurdahi, A.C.Parker, "REAL: a program for register allocation," Proc. 24th ACM/IEEE Design Automation Conf., pp.210-215, June 1987.

....along the critical path [ Delta Delta Delta ; S 3 ; S 4 ; Delta Delta Delta] the specification variable A is mapped to the register R 1 and along the critical path [ Delta Delta Delta ; S 7 ; S 8 ; Delta Delta Delta] it is mapped to R 3 . Many high level synthesis systems such as REAL [19], EMUCS [20] and EASY [21] are the systems which use value based register optimization techniques. Register optimization problem can be modeled as a channel routing problem; the life span of each value is modeled as a net interval. The minimum number of tracks corresponds to the number of ....

F. Kurdahi, A. Parker, "REAL: A Program for REgister ALlocation", 24th Design Automation Conference, pp. 210-215, 1987.

....subtasks as depicted in Figure 1. The specific subtasks addressed in this work are shaded. The work reported in this paper aims at completing the behavioral pipelined data path synthesis package Sehwa [4] and to integrate it with other synthesis tools developed by the authors, CSSP [6] and REAL [5]. In this paper we focus on the register transfer synthesis problem, specifically on the module assignment and interconnect sharing subtasks of RT level synthesis of pipelined data paths. Once a good module assignment and interconnect sharing schemes are obtained, the pipelined RT level design can ....

....stage will be very low) Once module assignment is complete and an interconnect sharing scheme is obtained, we need to complete the RT level design by adding more registers and multiplexors. In our approach, we perform optimal register assignment first using the register allocation procedure REAL [5]. Then the multiplexor placement is forced by the module assignment and the register assignment. 11 4.3 Example Since there has been no reported work on module assignment and interconnect sharing for pipelined designs, we cannot provide any comparative data on the performance of our approach. ....

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F. J. Kurdahi and A. C. Parker, "Real: a program for register allocation," in Proc. of the 24th Design Automation Conf., pp. 80--85, IEEE/ACM, July 1987.

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F. J. Kurdahi and A. C. Parker, "REAL: A program for register allocation, " oc. 24th Design Automation Conf., Miami Beach, FL, 1987, pp. 210--215.

No context found.

F. Kurdahi and A. Parker, "REAL: a program for REgister ALlocation," in Proc. Design Automation Conf., 1987, pp. 210--215.

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KURDAHI,F .J.AND PARKER, A. C. 1987. REAL: A program for REgister ALlocation. In Proceedings of the 24th ACM/IEEE Conference on Design Automation (DAC '87, Miami Beach, FL, June 28-July 1), A. O'Neill and D. Thomas, Eds. ACM Press, New York, NY, 210--215.

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F.J. Kurdahi and A.C. Parker, "REAL: A Program for Register Allocation," Proc. 24 Design Automation Conference, pp. 210-215, 1987.

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F.J. Kurdahi and A.C. Parker, "REAL: A Program for REgister ALlocation", Proc. 24th DAC, 1987, pp. 210-5

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