| P. Bannon. Alpha EV7: A Scalable Single-chip SMP. MicroProcessor Forum, October 1998. |
....an increasingly large fraction of execution, alternative mechanisms for exception handling become appealing. At the 1998 Microprocessor forum, Compaq presented a breakdown of the execution time of the transaction processing benchmark TPC C for their current and future Alpha based products [1]. The enhanced micro architecture of the out of order 21264 spent the same amount of time on trap handling as the in order 21164 (at the same frequency) but due to the 21264 s increased exploitation of ILP in the rest of the application the percentage contribution for traps increases from about 8 ....
P. Bannon. Alpha EV7: A Scalable Single-chip SMP. MicroProcessor Forum, October 1998.
....can yield worthwhile performance benefits. 4 Network Interface Placement The exact placement of the network interface within the system can have a significant impact on its performance. Systems have been designed with the network interface right on the CPU (the forthcoming DEC Compaq Alpha 21364 [4] or the MIT Message Driven Processor [11] the level 1 cache interface (MIT Alewife [1] the level 2 cache interface (MIT Star T NG [9] the memory bus (Stanford DASH [22] and FLASH [21] or the Sun WildFire [15] and the I O bus (DEC Compaq Memory Channel 2 [14] or Myrinet [6] Unfortunately, ....
P. Bannon. Alpha EV7: A scalable single-chip SMP. Seminar given at MicroProcessor Forum. Available at http://www.digital.com/alphaoem/ microprocessorforum.htm, Oct. 14, 1998.
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